Frequency synthesizer using an arithmetic frequency synthesizer and plural phase locked loops

Claim 1

A frequency synthesizer comprising: a phase locked loop comprising a first voltage controlled oscillator (VCO) for generating a signal e 1 of frequency f 1 and having a frequency control input, a divide-by-N divider to divide f 1 by N to produce a signal e N of frequency f 1 /N, a first phase detector responsive to e N and to a reference signal e r1 of frequency f r1 to produce a control signal e c1 , and means coupling e c1 to the frequency control input of said first VCO; a means for changing the value of N in said divider; a summing phase locked loop comprising a second VCO for generating a signal e 0 of frequency f 0 , and having a frequency control input, a subtractor for subtracting f 1 from f 0 to produce a signal e 2 of frequency f 2 =f 0 -f 1 , logic means including a second phase detector responsive to e 2 and a second reference signal e r2 to produce a second frequency control signal e c2 , and filter means responsive to e c2 for supplying a filtered e c2 ' to the frequency control input of said second VCO; and means for generating said second reference signal e r2 comprising: an accumulator containing digital data corresponding to the instantaneous phase of a waveform, said data contents being augmented by a selectable increment in response to each pulse of a clocking signal applied to said accumulator, said accumulator having overflow capability when said data contents are augmented beyond the capacity of said accumulator; means responsive to said data contents of said accumulator for providing a signal of frequency f AFS , said signal having said waveform and having period equal to the time between successive overflow occurrences of said accumulator; source means for providing a heterodyning signal of predetermined frequency; means responsive to said signal of frequency f AFS and to said heterodyning signal for generating a heterodyned signal having frequency f H which is the sum of f AFS and the frequency of said heterodyning signal; and means coupled to said heterodyned signal for dividing the frequency f H of said heterodyned signal by an integer M to produce said second reference signal e r2 of frequency f r2 .

Claim 9

A method of synthesizing frequencies by altering the frequency f 0 of the output signal e 0 of a voltage controlled oscillator (VCO) in response to a control signal e c2 comprising the steps of: augmenting by a selectable increment and at a predetermined rate the data contents of a digital accumulator; generating a signal e AFS having waveform corresponding to said data contents, wherein said selectable increment determines the frequency f AFS of said signal e AFS , said frequency f AFS being selectable within a first band of frequencies separated by MΔf, where M is a positive integer; combining signal e AFS with a heterodyning signal of predetermined frequency F H to produce a preliminary reference signal having frequency within a second band of frequencies which is the sum of F H and said first band of frequencies; dividing the frequency of said preliminary reference signal by M to produce a second reference signal e r2 having frequency within a third band of selectable frequencies separated by Δf; generating a signal e 1 having a frequency f 1 which is variable in steps of δf 1 , where δf 1 >>Δf; subtracting f 1 from f 0 to produce a signal e 2 of frequency f 2 ; and comparing the frequency and phase of e r2 and e 2 to produce the control signal e c2 .

Claim 10

A method of synthesizing frequencies by altering the frequency f 0 of the output signal e 0 of a voltage controlled oscillator (VCO) in response to a control signal e c2 comprising the steps of: augmenting by a selectable increment and at a predetermined rate the data contents of a digital accumulator; generating a signal e AFS having waveform corresponding to said data contents, wherein said selectable increment determines the frequency f AFS of said signal e AFS , said frequency f AFS being selectable within a first band of frequencies separated by MΔf, where M is a positive integer; combining signal e AFS with a heterodyning signal of predetermined frequency F H to produce a preliminary reference signal having frequency within a second band of frequencies which is the sum of F H and said first band of frequencies; dividing the frequency of said preliminary reference signal by M to produce a second reference signal e r2 having frequency within a third band of selectable frequencies separated by Δf; generating a signal e 1 having a frequency f 1 which is variable in steps of δf 1 , where δf 1 >>Δf; subtracting f 1 from f 0 to produce a signal e 2 of frequency f 2 ; and comparing the frequency and phase of e r2 and e 2 to produce the control signal e c2 .

Claim 11

A method of synthesizing frequencies by altering the frequency f 0 of the output of a voltage controlled oscillator (VCO) in response to a control signal e c2 comprising the steps of: generating a first signal e 1 having a frequency f 1 which is alterable in steps of δf; producing a second signal e 2 of frequency f 2 where f 2 =(f 0 -f 1 ); augmenting by a selectable increment and at a predetermined rate the data contents of a digital accumulator; generating a signal e AFS having waveform corresponding to said data contents, wherein said selectable increment determines the frequency f AFS of said signal e AFS , said frequency f AFS being selectable within a first band of frequencies separated by MΔf, where M is an integer; combining signal e AFS with a heterodyning signal of predetermined frequency F H to produce a preliminary reference signal having frequency Mf r2 within a second band of frequencies which is the sum of F H and said first band of frequencies; dividing the frequency of said preliminary reference signal by M to produce a second reference signal e r2 having frequency f r2 within a third selectable band of frequencies spaced apart by Δf; and comparing f 2 with f r2 to produce e c2 .

Claim 12

A method of synthesizing frequencies by altering the frequency f 0 of the output of a voltage controlled oscillator (VCO) in response to a control signal e c2 comprising the steps of: generating a first signal e 1 having a frequency f 1 which is alterable in steps of δf; producing a second signal e 2 of frequency f 2 where f 2 =(f 0 -f 1 ); augmenting by a selectable increment and at a predetermined rate the data contents of a digital accumulator; generating a signal e AFS having waveform corresponding to said data contents, wherein said selectable increment determines the frequency f AFS of said signal e AFS , said frequency f AFS being selectable within a first band of frequencies separated by MΔf, where M is an integer; combining signal e AFS with a heterodyning signal of predetermined frequency F H to produce a preliminary reference signal having frequency Mf r2 within a second band of frequencies which is the sum of F H and said first band of frequencies; dividing the frequency of said preliminary reference signal by M to produce a second reference signal e r2 having frequency f r2 within a third selectable band of frequencies spaced apart by Δf; and comparing f 2 with f r2 to produce e c2 .