US4039806A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synthesizer for testing elements of a geophysical data acquisition system
Assignee: Chevron USA Inc
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Filing: 1975-10-01
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Granted: 1977-08-02
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Expires: 1995-10-01
Abstract
Abstract This disclosure relates to a non-recursive digital synthesizer for producing a surprisingly accurate synthesized sinusoid suitable for testing elements of a geophysical data acquisition system in either a laboratory or a field environment. In accordance with the present invention, [(C/2)+1]-discrete--16-bit binary words are stored in a read-only memory (ROM), representing discrete amplitudes of a digitized sinusoid in a frequency range of 1-500 Hz, and then accessed in succession to a digital-to-analog converter (DAC). A separate suppression circuit means at the output of the DAC is adapted to operate in synchronization with movement of the binary words through the DAC; in that way, glitches generated by the various digital elements of the synthesizer are suppressed. Result: accuracy of the generated sinusoid to the elements under test is assured.
Inventors
- 👤 Oke A. Fredriksson
- 👤 Elmer L. Thomas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:03
CPC Classifications
G; G01; G01V; G01V1/00; G01V1/16; G01V13/00; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/035; G06F2101/00; G06F2101/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
241 words
A synthesizer used in testing elements of a geophysical data acquisition system using a generated synthesized sinusoid of frequency f o where f o is in a range of 1 to 500 Hz, comprising: means for producing a pulse train having a rate equal to Cf o where C is a constant; counter means operative in response to said pulse train for producing a series of addresses; storage means connected to said counter means, having storage locations operative in response to said addresses to produces a series of binary code words, each indicative of a digital amplitude of said sinusoid as a function of time; digital-to-analog conversion (DAC) means connected to said storage means and having an output conductor path, for producing discrete analog amplitude values of said sinusoid thereat corresponding to said binary code words accessed from said storage means; and glitch suppression means connected to said conductor path of said DAC means operative to hold said discrete analog amplitude values at individual true values at least during a selected time interval measured by a change in operating state of said conductor path whereby unwanted glitches produced by change in operational state of at least said DAC means are suppressed; said suppression circuit including a one-shot enabled by said Cf o pulse train, and switch circuit means responsive to said enabled one-shot to selectively disable and then enable said conductor path from said DAC means during said selected time interval.
Claim 2
Dependent Claim
241 words
A synthesizer used in testing elements of a geophysical data acquisition system using a generated synthesized sinusoid of frequency f o where f o is in a range of 1 to 500 Hz, comprising: means for producing a pulse train having a rate equal to Cf o where C is a constant; counter means operative in response to said pulse train for producing a series of addresses; storage means connected to said counter means, having storage locations operative in response to said addresses to produces a series of binary code words, each indicative of a digital amplitude of said sinusoid as a function of time; digital-to-analog conversion (DAC) means connected to said storage means and having an output conductor path, for producing discrete analog amplitude values of said sinusoid thereat corresponding to said binary code words accessed from said storage means; and glitch suppression means connected to said conductor path of said DAC means operative to hold said discrete analog amplitude values at individual true values at least during a selected time interval measured by a change in operating state of said conductor path whereby unwanted glitches produced by change in operational state of at least said DAC means are suppressed; said suppression circuit including a one-shot enabled by said Cf o pulse train, and switch circuit means responsive to said enabled one-shot to selectively disable and then enable said conductor path from said DAC means during said selected time interval.
Claim 3
Dependent Claim
67 words
The synthesizer of claim 1 in which said switch circuit means includes a multistate switch in series with a sample-and-hold capacitor and said DAC means, said switch circuit means disabling said path for said selected time interval, said selected time interval being of sufficient length so that glitches occasioned by change in state of said DAC means decay to acceptable levels before said path is again enabled.
Claim 4
Dependent Claim
20 words
The synthesizer of claim 2 in which charge of said sample-and-hold capacitor remains essentially constant during said selected time interval.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-01 | 1981-01-31 | 1981-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-01 | 1985-01-31 | 1985-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-01 | 1989-01-31 | 1989-08-02 | $7700.00 | Window Closed / Lapsed |