Phase locked loop circuit with false locking detector and a lock acquisition sweep

Assignee: Alcatel Lucent NV

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Filing: 1996-03-27

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Granted: 1997-09-23

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Expires: 2016-03-27

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Abstract

Abstract Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order to avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of, which is added in an adder circuit (ADD) to that coming from the first loop, for producing voltage pulses when both signals are not at the same frequency, provoking a non-locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.

Inventors

👤 Francisco Manuel Garcia Palancar

Bibliographic Details

Application Number —

Jurisdiction US

Data Source google_patents

Last Synchronized 2026-10-29 11:12

CPC Classifications

H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H04L7/02; H04L7/033; H03L2207/00; H03L2207/14; H03L7/085; H03L7/087; H03L7/089; H03L7/0891; Y; Y10; Y10S; Y10S331/00; Y10S331/02

Claims Analysis

Total Claims: 4

Claim 1

Independent Claim 126 words

Clock recovery circuit for an incoming data signal (DS) comprising a first phase locked loop (PC1, CP1, VCXO) comprising a first charge pump (CP1) having an output voltage which increases or decreases depending on output pulses from a first phase comparator (PC1), characterized in that a voltage-controlled oscillator (VCXO) of the first phase locked loop receives a signal coming from a false locking detector (FLD) which, in turn, receives the incoming data signal (DS) and a signal derived from an output of the voltage-controlled oscillator (VCXO), the false locking detector (FLD) comprising a second phase comparator (PC2) and a second charge pump (CP2) having an output signal for summation with said output voltage of the first charge pump (CP1) for control of the voltage-controlled oscillator (VCXO).

Claim 2

Dependent Claim 126 words

Claim 3

Dependent Claim 44 words

Clock recovery circuit according to claim 1, characterized in that it also has discharge circuits (DC1, DC2) which discharge, respectively, capacitors of the first and second charge pumps (CP1, CP2) when the output signal from the second charge pump (CP2) reaches a determined value.

Claim 4

Dependent Claim 53 words

Clock recovery circuit according to claim 1, characterized in that the output signal from the second phase comparator (PC2) of the false locking detector (FLD) adopts a high level when a difference in times between transitions of the data signal and activating edges of a recovered data clock signal exceeds a determined value.

References Cited (Backward Citations)

US3909735A Cited

US4087628A Cited

US4100503A Cited

US4213096A Cited

US4297650A Cited

JPS5635561A Cited

US4590602A Cited

US5012494A Cited

JPH06132818A Cited

GB2280555A Cited

US5485484A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-09-22	2001-03-24	2001-09-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-09-22	2005-03-24	2005-09-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-09-22	2009-03-24	2009-09-23	$7700.00	Window Closed / Lapsed

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