Method and apparatus for clock recovery and data retiming for random NRZ data

Claim 2

Apparatus for recovering a clock signal from a random NRZ data signal, comprising: a phase detector for detecting the phase difference between said random NRZ data signal and a clock signal and for generating a phase signal representative of said phase difference wherein said phase signal comprises a binary signal having first and second logic levels, said first logic level being representative of said clock signal having an early phase relationship with said data signal and said second logic level being representative of said clock signal having a late phase relationship with said data signal; an integrator, connected to receive said phase signal, for integrating said phase signal over a period of time and for generating an integration signal representative of the integration of said phase signal; and an oscillator, connected to receive said integration signal and said phase signal, for generating said clock signal at a clock frequency responsive to said phase signal and said integration signal wherein said clock frequency is determined by a centering factor and an offset factor said centering factor being controlled by said integration signal and said offset factor being controlled by said phase signal.

Claim 3

The apparatus of claim 1, wherein said oscillator comprises generator means having a first time delay for generating a preliminary clock signal and delay means having a second time delay for receiving said preliminary clock signal and providing said preliminary clock signal at an output in relation to said time delay, wherein said integration signal controls the length of said first time delay, wherein said phase signal controls the length of said second time delay and wherein said generator means and said delay means are arranged in a loop.

Claim 4

The apparatus of claim 2, wherein said first generator means comprises a plurality of signal processors connected in series and connected to receive said integration signal, wherein said integration signal controls the time delay of each signal processor.

Claim 5

The apparatus of claim 3, wherein each of said signal processors comprises an invertor.

Claim 6

The apparatus of claim 1, wherein said phase signal is termed v 1 , said integration signal is termed v 2 and wherein said oscillator generates said clock signal at a frequency (f c ) substantially similar with the following: ##EQU2##

Claim 7

The apparatus of claim 2, wherein said second time delay comprises first and second time periods, wherein said second time delay takes the value of said first time period when said phase signal is representative of an early phase relationship and wherein said second time delay takes the value of said second time period when said phase signal is representative of a late phase relationship.

Claim 10

The method of claim 7, wherein said step of generating said clock signal comprises the steps generating a preliminary clock signal by generator means having a first time delay and delaying said preliminary clock signal in delay means having a second time delay wherein said integration signal controls the length of said first time delay, wherein said phase signal controls the length of said second time delay and wherein the output of said delay means is said clock signal.

Claim 11

The method of claim 8, wherein said first generator means comprises a plurality of signal processors connected in series and connected to receive said integration signal, wherein said integration signal controls the time delay of each signal processor.

Claim 12

The method of claim 9, wherein each of said signal processors comprises an invertor.

Claim 13

The method of claim 7, wherein said phase signal is termed v 1 , said integration signal is termed v 2 and wherein said step of generating said clock signal generates said clock signal at a frequency (f c ) substantially similar with the following: ##EQU3##

Claim 14

The method of claim 8, wherein said second time delay comprises first and second time periods, wherein said step of delaying said preliminary clock signal comprises the step of utilizing said first time period as said second time delay when said phase signal is representative of an early phase relationship and utilizing said second time period as said second time delay when said phase signal is representative of a late phase relationship.

Claim 15

A phase detector for detecting the phase difference between a random NRZ data signal and a clock signal, comprising: sampling means, connected to receive said clock signal and said data signal, for sampling said data signal in response to said clock signal and for generating a number of consecutive samples of said data signal; and determination means, connected to said sampling means, for determining whether the phase of said clock signal is definite or indefinite in relation to said consecutive samples, for assigning a definite phase relationship whenever said phase is determined to be indefinite, wherein phase assignment is made in response to the frequency relationship between said data signal and said clock signal, and for generating a phase signal representative of the determined phase relationships.

Claim 16

A phase detector for detecting the phase difference between a random NRZ data signal and a clock signal, comprising: sampling means, connected to receive said clock signal and said data signal, for sampling said data signal in response to said clock signal and for generating a number of consecutive samples of said data signal; and determination means, connected to said sampling means, for determining whether the phase of said clock signal is definite or indefinite in relation to said consecutive samples, for assigning a definite phase relationship whenever said phase is determined to be indefinite, wherein phase assignment is made in response to the frequency relationship between said data signal and said clock signal, and for generating a phase signal representative of the determined phase relationships.

Claim 17

The apparatus of claim 13, wherein the definite phase of said clock signal is either the early phase or the late phase and wherein the indefinite phase of said clock signal is the slip state.

Claim 18

The apparatus of claim 14, wherein the means for assigning a definite phase relationship to said clock signal comprises skew means for skewing the assignment of a definite phase relationship of said clock signal towards either the early phase or the late phase.

Claim 19

The apparatus of claim 15, wherein said skew means assigns the last phase relationship determined by said determination means when it is determined that said clock signal is in the slip state.

Claim 20

The apparatus of claim 16, wherein said phase signal comprises a binary signal having first and second logic levels, said first logic level being representative of said clock signal having an early phase relationship and said second logic level being representative of said clock signal having a late phase relationship and wherein said skew means comprises a latch for storing said binary signal.

Claim 21

The apparatus of claim 17, wherein said consecutive samples comprises first second and third samples and wherein said means for determining whether said clock is definite or indefinite comprises first and second exclusive OR gates, wherein said first and second samples are provided to the inputs of said first exclusive OR gate and wherein said first and third samples are provided to the inputs of said second exclusive OR gate, wherein the output of said second exclusive OR gate and the output of said latch are provided to the inputs of a first NAND gate, and wherein the output of said first exclusive OR gate and said first NAND gate are provided to the input of a second NAND gate.

Claim 24

The method of claim 19, wherein the definite phase of said clock signal is either the early phase or the late phase and wherein the indefinite phase of said clock signal is the slip state.

Claim 25

The method of claim 20, wherein the step of assigning a definite phase relationship to said clock signal comprises the step of skewing the assignment of a definite phase relationship of said clock signal towards either the early phase or the late phase.

Claim 26

The method of claim 21, wherein the step of assigning a definite phase relationship to said clock signal comprises assigning the last determined phase relationship when it is determined that said clock signal is in the slip state.

Claim 27

Apparatus for recovering a clock signal from a random NRZ data signal, comprising: a phase detector for detecting the phase difference between said random NRZ data signal and a clock signal and for generating a phase signal representative of said phase difference wherein said phase detector comprises sampling means, connected to receive said clock signal and said data signal, for sampling said data signal in response to said clock signal and for generating a number of consecutive samples of said data signal and determination means, connected to said sampling means, for determining whether the phase of said clock signal is definite or indefinite in relation to said consecutive samples, for assigning a definite phase relationship whenever said phase is determined to be indefinite and for generating a phase signal representative of the determined phase relationships; an integrator, connected to receive said phase signal, for integrating said phase signal over a period of time, said integrator comprising summing means for summing said phase signal with a feedback signal and for providing the summed signal to an output, charging means, connected to said output, for storing said summed signal and for providing the summed signal voltage at an output and buffer means, connected to said summing means and said charging means, for providing said feedback signal to said summing means, wherein said feedback signal is representative of said summed signal voltage stored in said charging means wherein said charging means generates an integration signal representative of the signal stored in said charging means; and an oscillator, connected to receive said integration signal and said phase signal, for generating said clock signal at a clock frequency responsive to said phase signal and said integration signal, said oscillator comprising generator means having a first time delay for generating a preliminary clock signal and delay means, having an input and an output, for reproducing at said output said preliminary clock signal provided to said input within a second time delay, wherein the length of said second time delay is controlled by a control signal and control means, connected to said delay means, for generating said control signal in response to said phase signal so that said time delay has the value of a first time period when said phase signal is representative of an early phase relationship and so that said time delay has the value of a second time period when said phase signal is representative of a late phase relationship.

Claim 28

Apparatus for recovering a clock signal from a random NRZ data signal, comprising: a phase detector for detecting the phase difference between said random NRZ data signal and a clock signal and for generating a phase signal representative of said phase difference wherein said phase detector comprises sampling means, connected to receive said clock signal and said data signal, for sampling said data signal in response to said clock signal and for generating a number of consecutive samples of said data signal and determination means, connected to said sampling means, for determining whether the phase of said clock signal is definite or indefinite in relation to said consecutive samples, for assigning a definite phase relationship whenever said phase is determined to be indefinite and for generating a phase signal representative of the determined phase relationships; an integrator, connected to receive said phase signal, for integrating said phase signal over a period of time, said integrator comprising summing means for summing said phase signal with a feedback signal and for providing the summed signal to an output, charging means, connected to said output, for storing said summed signal and for providing the summed signal voltage at an output and buffer means, connected to said summing means and said charging means, for providing said feedback signal to said summing means, wherein said feedback signal is representative of said summed signal voltage stored in said charging means wherein said charging means generates an integration signal representative of the signal stored in said charging means; and an oscillator, connected to receive said integration signal and said phase signal, for generating said clock signal at a clock frequency responsive to said phase signal and said integration signal, said oscillator comprising generator means having a first time delay for generating a preliminary clock signal and delay means, having an input and an output, for reproducing at said output said preliminary clock signal provided to said input within a second time delay, wherein the length of said second time delay is controlled by a control signal and control means, connected to said delay means, for generating said control signal in response to said phase signal so that said time delay has the value of a first time period when said phase signal is representative of an early phase relationship and so that said time delay has the value of a second time period when said phase signal is representative of a late phase relationship.