Wide range clock recovery circuit

Claim 2

A wide frequency range, random variable data rate clock signal recovey circuit for digital data communications receiver comprising: data input means for receiving input data signals; phase lock loop means connected to said data input means and receiving input signals therefrom for clock signal recovery and including voltage controlled oscillator means for generating output signals and signals utilized within said phase lock loop means and phase detector means having at least a first input from said data input means and a second input from said voltage controlled oscillator means for comparing the phase of said first and second input signals and outputting signals to said voltage controlled oscillator means representative of the difference between said first and second input signals; means for generating reference signals distinct from the output of said voltage controlled oscillator means; frequency synthesizer means receiving as inputs said reference signals and output signals of said voltage controlled oscillator means and being connected in a loop with said voltage controlled oscillator means of said phase lock loop means for initially controlling said voltage controlled oscillator means to produce signals which estimate the frequencies of said input data signals to a level of accuracy within the seizure bandwidth of said phase lock loop means; and lock detector means having at least a first input from said data input means and a second input from said voltage controlled oscillator means for producing a signal to said frequency synthesizer means for disabling the output of said frequency synthesizer means in response to the difference between said first and second input signals to said lock detector means being within said bandwidth of said phase lock loop means.

Claim 3

The wide range clock recovery circuit according to claim 1, wherein said level of accuracy is determined by the frequency of said reference signals.

Claim 4

The wide range clock recovery circuit according to claim 1, wherein said frequency synthesizer means includes means for receiving user input signals representative of estimates of said input data signal frequencies and controlling the frequency output of said voltage controlled oscillator means in response to said user input signals to produce said estimates of the data signal frequencies.

Claim 5

The wide range clock recovery circuit according to claim 1, wherein said voltage-controlled oscillator means includes a narrow range oscillator means for generating output signal frequencies and a frequency divider means connected to said narrow range oscillator means for generating divided signal frequencies from said output signals of said narrow range oscillator means.

Claim 6

The wide range clock recovery circuit according to claim 4, wherein said voltage controlled oscillator means further includes range selector means for controlling the dividing factor of said frequency divider means.

Claim 7

The wide range clock recovery circuit according to claim 1, wherein said data input means receives non return to zero input data signals.

Claim 8

The wide range clock recovery circuit according to claim 6, wherein said data input means includes programmable monostable means for processing said non return to zero input data signals to provide discrete output pulses for each data signal transition.

Claim 9

A wide frequency range, random variable data rate clock signal recovery circuit for a digital data communications receiver comprising: data input means for receiving input data signals; phase lock loop means connected to said data input means and receiving input signals therefrom for clock signal recovery and including voltage controlled oscillator means for generating output signals and signals utilized within said phase lock loop means; frequency synthesizer means also including said voltage controlled oscillator means of said phase lock loop means and connected thereto for initially controlling said voltage controlled oscillator means to produce signals which estimate the frequencies of said input data signals to a level of accuracy within the seizure bandwidth of said phase lock loop means; and said frequency synthesizer means including reference signal oscillator means for generating reference signal frequencies, wide range voltage controlled oscillator means for generating particular signal frequencies as a function of control input signals, frequency divider means for generating divided signal frequencies from said signal frequencies produced by said wide range voltage controlled oscillator means, frequency detector means for comparing said reference frequencies with said divided signal frequencies and generating output signals representative of the frequency differences therebetween, and the loop filter means for generating said control input signals for said wide range voltage controlled oscillator means in response to said output signals from said frequency detector means.

Claim 10

A wide frequency range, random variable data rate clock signal recovery circuit for a digital data communications receiver comprising: data input means for receiving input data signals; phase lock loop means connected to said data input means and receiving input signals therefrom for clock signal recovery and including voltage controlled oscillator means for generating output signals and signals utilized within said phase lock loop means; frequency synthesizer means also including said voltage controlled oscillator means of said phase lock loop means and connected thereto for initially controlling said voltage controlled oscillator means to produce signals which estimate the frequencies of said input data signals to a level of accuracy within the seizure bandwidth of said phase lock loop means; and said frequency synthesizer means including reference signal oscillator means for generating reference signal frequencies, wide range voltage controlled oscillator means for generating particular signal frequencies as a function of control input signals, frequency divider means for generating divided signal frequencies from said signal frequencies produced by said wide range voltage controlled oscillator means, frequency detector means for comparing said reference frequencies with said divided signal frequencies and generating output signals representative of the frequency differences therebetween, and the loop filter means for generating said control input signals for said wide range voltage controlled oscillator means in response to said output signals from said frequency detector means.

Claim 11

The wide range clock recovery circuit according to claim 8, wherein said frequency synthesizer means provides single loop realization without signal mixing, and wherein said frequency divider means is user programmable to divide the output of said wide-range voltage controlled oscillator means by a user input factor of m, where m is representative of the user estimate of said input data signal frequencies.

Claim 12

A wide range signal recovery circuit comprising: input means for receiving data signals; voltage controlled oscillator means for generating data approximating signals; means for generating reference signals; frequency detector means responsive to said data approximating signals and said reference signals for controlling the output of said voltage controlled oscillator means; lockout means responsive to said data signals and said data approximating signals for disabling the control of said voltage controlled oscillator means by said frequency detector means when the difference between said data signals and said data approximating signals reaches a predetermined level; and phase detector means responsive to said data signals and said data approximating signals for controlling the output of said voltage controlled oscillator means when control by said frequency detector means is disabled.

Claim 13

A wide range signal recovery circuit comprising: input means for receiving data signals; voltage controlled oscillator means for generating data approximating signals; means for generating reference signals; frequency detector means responsive to said data approximating signals and said reference signals for controlling the output of said voltage controlled oscillator means; lockout means responsive to said data signals and said data approximating signals for disabling the control of said voltage controlled oscillator means by said frequency detector means when the difference between said data signals and said data approximating signals reaches a predetermined level; and phase detector means responsive to said data signals and said data approximating signals for controlling the output of said voltage controlled oscillator means when control by said frequency detector means is disabled.

Claim 14

A wide frequency range, random variable data rate clock signal recovery circuit for a digital data communications receiver comprising: data input means for receiving input data signals; phase lock loop means connected to said data input means and receiving input signals therefrom for clock signal recovery and including voltage controlled oscillator means; frequency synthesizer means also including said voltage controlled oscillator means of said phase lock loop means and connected thereto for initially controlling said voltage controlled oscillator means to produce signals which estimate frequencies of said input data signals to a level of accuracy within the seizure bandwidth of said phase lock loop means; said frequencies synthesizer means including reference signal oscillator means for generating reference signal frequencies, wide range voltage controlled oscillator means for generating particular signal frequencies as a function of control input signals, frequency divider means for generating divided signal frequencies from said signal frequencies produced by said wide range voltage controlled oscillator means, frequency detector means for comparing said reference frequencies with said divided signal frequencies and generating output signals representative of the frequency differences therebetween, and loop filter means for generating said control input signals for said wide range voltage controlled oscillator means in response to said output signals from said frequency detector means; and said wide range voltage controlled oscillator means including a narrow range voltage controlled oscillator means for generating signal frequencies, a second frequency divider means coupled to the output of said narrow range voltage controlled oscillator means for generating divided frequencies of said signal frequencies of said narrow range voltage controlled oscillator means, and an autoranging means for controlling the dividing factors of said frequency divider means.

Claim 15

A wide frequency range, random variable data rate clock signal recovery circuit for a digital data communications receiver comprising: data input means for receiving input data signals; phase lock loop means connected to said data input means and receiving input signals therefrom for clock signal recovery and including voltage controlled oscillator means; frequency synthesizer means also including said voltage controlled oscillator means of said phase lock loop means and connected thereto for initially controlling said voltage controlled oscillator means to produce signals which estimate frequencies of said input data signals to a level of accuracy within the seizure bandwidth of said phase lock loop means; said frequencies synthesizer means including reference signal oscillator means for generating reference signal frequencies, wide range voltage controlled oscillator means for generating particular signal frequencies as a function of control input signals, frequency divider means for generating divided signal frequencies from said signal frequencies produced by said wide range voltage controlled oscillator means, frequency detector means for comparing said reference frequencies with said divided signal frequencies and generating output signals representative of the frequency differences therebetween, and loop filter means for generating said control input signals for said wide range voltage controlled oscillator means in response to said output signals from said frequency detector means; and said wide range voltage controlled oscillator means including a narrow range voltage controlled oscillator means for generating signal frequencies, a second frequency divider means coupled to the output of said narrow range voltage controlled oscillator means for generating divided frequencies of said signal frequencies of said narrow range voltage controlled oscillator means, and an autoranging means for controlling the dividing factors of said frequency divider means.

Claim 16

A wide frequency range, random variable data rate clock signal recovery circuit for a digital data communications receiver comprising: data input means for receiving input data signals; phase lock loop means connected to said data input means and receiving input signals therefrom for clock signal recovery and including voltage controlled oscillator means; frequency synthesizer means also including said voltage controlled oscillator means of said phase lock loop means and connected thereto for initially controlling said voltage controlled oscillator means to produce signals which estimate frequencies of said input data signals to a level of accuracy within the seizure bandwidth of said phase lock loop means; said frequencies synthesizer means including reference signal oscillator means for generating reference signal frequencies, wide range voltage controlled oscillator means for generating particular signal frequencies as a function of control input signals, frequency divider means for generating divided signal frequencies from said signal frequencies produced by said wide range voltage controlled oscillator means, frequency detector means for comparing said reference frequencies with said divided signal frequencies and generating output signals representative of the frequency differences therebetween, and loop filter means for generating said control input signals for said wide range voltage controlled oscillator means in response to said output signals from said frequency detector means; and said phase lock loop means including phase detector means having at least a first input from said data input means and a second input from said voltage controlled oscillator means for comparing the phase of said first and second input signals and outputting signals to said loop filter means representative of the difference between said first and second input signals, and lock detector means having at least a first input from said data input means and a second input from said voltage controlled oscillator means for producing a signal to said frequency detector for disabling the output of said frequency detector in response to the difference between said first and second input signals to said lock detector means being within said bandwith of said phase lock loop means.

Claim 17

A wide frequency range, random variable data rate clock signal recovery circuit for a digital data communications receiver comprising: data input means for receiving input data signals; phase lock loop means connected to said data input means and receiving input signals therefrom for clock signal recovery and including voltage controlled oscillator means; frequency synthesizer means also including said voltage controlled oscillator means of said phase lock loop means and connected thereto for initially controlling said voltage controlled oscillator means to produce signals which estimate frequencies of said input data signals to a level of accuracy within the seizure bandwidth of said phase lock loop means; said frequencies synthesizer means including reference signal oscillator means for generating reference signal frequencies, wide range voltage controlled oscillator means for generating particular signal frequencies as a function of control input signals, frequency divider means for generating divided signal frequencies from said signal frequencies produced by said wide range voltage controlled oscillator means, frequency detector means for comparing said reference frequencies with said divided signal frequencies and generating output signals representative of the frequency differences therebetween, and loop filter means for generating said control input signals for said wide range voltage controlled oscillator means in response to said output signals from said frequency detector means; and said phase lock loop means including phase detector means having at least a first input from said data input means and a second input from said voltage controlled oscillator means for comparing the phase of said first and second input signals and outputting signals to said loop filter means representative of the difference between said first and second input signals, and lock detector means having at least a first input from said data input means and a second input from said voltage controlled oscillator means for producing a signal to said frequency detector for disabling the output of said frequency detector in response to the difference between said first and second input signals to said lock detector means being within said bandwith of said phase lock loop means.