US3959601A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable rate clock signal recovery circuit
Assignee: Lockheed Martin Tactical Systems Inc
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Filing: 1975-06-27
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Granted: 1976-05-25
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Expires: 1995-06-27
Abstract
Abstract A circuit for use in a digital data receiver to recover a clock signal, of variable rate, from the signal received by the receiver. A typical digital data receiver includes demodulating or other means for converting the received signal to a binary data signal having a characteristic which changes in a manner corresponding to transition in the digital data received. The invention provides circuit means for recovering a clock signal from the binary data signal where the data rate may vary over a substantial range. The clock signal recovery circuit utilizes a logic transition detector to produce a narrow pulse at each data transition in the binary data signal. The pulses, which contain harmonic frequencies at the clock rate of the binary data signal, are up-converted or mixed with an electrical signal from a frequency synthesizer. The signal resulting from this up-conversion is filtered by a narrow-band filter to produce an electrical signal at a predetermined intermediate frequency. The output signal from the frequency synthesizer is mixed with the signal from the narrow-band filter, in a down-converter circuit, to produce a reference signal having a frequency proportional to the clock frequency of the binary data signal. The frequency synthesizer has a variable frequency output determined by the setting of a data rate selector. An electronically controlled oscillator produces a signal having a frequency proportional to the binary-data-signal clock rate. The oscillator is in a phase-lock loop including a phase detector supplied with the reference signal having a frequency proportional to the clock rate of the binary data signal.
Inventors
- 👤 Benjamin Olevsky
- 👤 Jay W. Layer
- 👤 Keith L. Zerschling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:55
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
242 words
A variable-rate clock-signal recovery circuit for a digital data receiver, said digital data receiver including means for generating a binary data signal having a characteristic which changes in a manner corresponding to transitions in the digital data received by said receiver, said variable-rate clock-signal recovery circuit comprising: first circuit means, supplied with said binary data signal, for generating a first electrical signal comprising a series of pulses, each of said pulses corresponding to a transition in the digital data received by said receiver; second circuit means for generating a second electrical signal of predetermined or selectable frequency; third circuit means, supplied with said first and second electrical signals, for mixing said first and second electrical signals and up-converting said first electrical signal to produce a third electrical signal having side-band or spectral components differing in frequency from said second electrical signal by the spectral content of said first electrical signal; fourth circuit means, supplied with said third electrical signal, for producing a fourth electrical signal of predetermined frequency, said fourth circuit means filtering said third electrical signal; fifth circuit means, supplied with said second electrical signal and with said fourth electrical signal or a signal derived therefrom for mixing or down-converting said fourth electrical signal or signal derived therefrom to produce a fifth electrical signal having a frequency corresponding to the difference in frequencies of said second and fourth electrical signals and proportional to the clock rate of said binary data signal.
Claim 2
Dependent Claim
242 words
A variable-rate clock-signal recovery circuit for a digital data receiver, said digital data receiver including means for generating a binary data signal having a characteristic which changes in a manner corresponding to transitions in the digital data received by said receiver, said variable-rate clock-signal recovery circuit comprising: first circuit means, supplied with said binary data signal, for generating a first electrical signal comprising a series of pulses, each of said pulses corresponding to a transition in the digital data received by said receiver; second circuit means for generating a second electrical signal of predetermined or selectable frequency; third circuit means, supplied with said first and second electrical signals, for mixing said first and second electrical signals and up-converting said first electrical signal to produce a third electrical signal having side-band or spectral components differing in frequency from said second electrical signal by the spectral content of said first electrical signal; fourth circuit means, supplied with said third electrical signal, for producing a fourth electrical signal of predetermined frequency, said fourth circuit means filtering said third electrical signal; fifth circuit means, supplied with said second electrical signal and with said fourth electrical signal or a signal derived therefrom for mixing or down-converting said fourth electrical signal or signal derived therefrom to produce a fifth electrical signal having a frequency corresponding to the difference in frequencies of said second and fourth electrical signals and proportional to the clock rate of said binary data signal.
Claim 3
Dependent Claim
44 words
A variable-rate clock-signal recovery circuit according to claim 1 wherein said second circuit means comprises a data rate selector and a frequency synthesizer, said frequency synthesizer generating said second electrical signal and said data rate selector controlling the frequency of said second electrical signal.
Claim 4
Dependent Claim
142 words
A variable-rate clock-signal recovery circuit according to claim 2 which further comprises an electronically-controlled oscillator for generating a sixth electrical signal of variable frequency; and a phase detector supplied with said fifth electrical signal or a signal derived therefrom and with a signal having a frequency proportional to the frequency of said sixth electrical signal produced by said electronically-controlled oscillator, said phase detector generating a seventh electrical signal having a characteristic governed by the magnitude of the phase difference between said signals supplied to said phase detector, said seventh electrical signal being supplied to said electronically-controlled oscillator to adjust the frequency of said sixth electrical signal to reduce said phase difference between said signals supplied to said phase detector, said sixth electrical signal thereby having a frequency proportional to the clock rate corresponding to the data rate of said binary data signal.
Claim 5
Dependent Claim
42 words
A variable rate clock signal recovery circuit according to claim 3 which further includes a variable gain amplifier interposed between said electronically-controlled oscillator and said phase detector for amplifying said seventh electrical signal supplied by said phase detector to said electronically-controlled oscillator.
Claim 6
Dependent Claim
35 words
A variable-rate clock-signal recovery circuit according to claim 4 wherein said variable gain amplifier is coupled to said data rate selector, the gain of said variable gain amplifier being controlled by said data rate selector.
Claim 7
Dependent Claim
69 words
A variable-rate clock-signal recovery circuit according to claim 4 which further includes a switch having a plurality of input terminals and an output terminal, said output terminal being selectively coupled to said input terminals, said input terminals being supplied with said sixth electrical signal and with at least an eighth electrical signal having a frequency equal to the frequency of said sixth electrical signal divided by a whole number.
Claim 8
Dependent Claim
69 words
A variable-rate clock-signal recovery circuit according to claim 5 which further includes a switch having a plurality of input terminals and an output terminal, said output terminal being selectively coupled to said input terminals, said input terminals being supplied with said sixth electrical signal and with at least an eighth electrical signal having a frequency equal to the frequency of said sixth electrical signal divided by a whole number.
Claim 9
Dependent Claim
36 words
A variable-rate clock-signal recovery circuit according to claim 6 wherein said switch is coupled to said data rate selector, said data rate selector controlling the connection of said switch output terminal to said switch input terminals.
Claim 10
Dependent Claim
36 words
A variable-rate clock-signal recovery circuit according to claim 7 wherein said switch is coupled to said data rate selector, said data rate selector controlling the connection of said switch output terminal to said switch input terminals.
Claim 11
Dependent Claim
48 words
A variable-rate clock-signal recovery circuit according to claim 9 wherein said signal said to be supplied to said phase detector and said to have a frequency proportional to the frequency of said sixth electrical signal, is derived from the signal appearing on said output terminal of said switch.
References Cited (Backward Citations)
US3238462A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-25 | 1979-11-24 | 1980-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-25 | 1983-11-24 | 1984-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-25 | 1987-11-24 | 1988-05-25 | $7700.00 | Window Closed / Lapsed |