Method for fabricating a deep submicron mosfet device using an in-situ polymer spacer to decrease device channel length

Claim 1

A method of fabricating a MOSFET device, on a semiconductor substrate, with a local threshold voltage adjust region, comprising the steps of: depositing a first dielectric layer on said semiconductor substrate; forming a photoresist pattern, in a photoresist layer, on said first dielectric layer, with a narrow opening in said photoresist layer, exposing top surface of said first dielectric layer; forming polymer spacers on the sides of said narrow opening in said photoresist layer, creating a polymer coated opening, in said photoresist layer; forming a narrow hole opening in said first dielectric layer by etching of said first dielectric layer, using said photoresist pattern, with said polymer coated opening, as a mask; removal of said photoresist pattern, and of said polymer spacers; ion implanting a first conductivity imparting dopant, into an area of said semiconductor substrate, exposed in said narrow hole opening in said first dielectric layer, to create said local threshold adjust region; growing a gate insulator layer on said semiconductor substrate, exposed in said narrow hole opening in said first dielectric layer; depositing a polysilicon layer, completely filling said narrow hole opening in said first dielectric layer; planarization of said polysilicon layer, by removal of said polysilicon layer from top surface of said first dielectric layer, forming a polysilicon gate structure in said narrow hole opening in said first dielectric layer; removal of a top portion of said first dielectric layer; complete removal of said first dielectric layer, exposing all surfaces of said polysilicon gate structure; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to form a lightly doped source and drain region; depositing a first insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said first insulator layer, to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a second insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said second insulator layer, to expose top surface of said heavily doped source and drain region, and to expose top surface of said polysilicon gate structure; depositing a metal layer on top surface of said second insulator layer, on top surface of said heavily doped source and drain region, and on top surface of said polysilicon gate structure, exposed in said contact hole; and patterning of said metal layer, to form metal contact structures to said heavily doped source and drain region, and to said polysilicon gate structure.

Claim 2

A method of fabricating a MOSFET device, on a semiconductor substrate, with a local threshold voltage adjust region, comprising the steps of: depositing a first dielectric layer on said semiconductor substrate; forming a photoresist pattern, in a photoresist layer, on said first dielectric layer, with a narrow opening in said photoresist layer, exposing top surface of said first dielectric layer; forming polymer spacers on the sides of said narrow opening in said photoresist layer, creating a polymer coated opening, in said photoresist layer; forming a narrow hole opening in said first dielectric layer by etching of said first dielectric layer, using said photoresist pattern, with said polymer coated opening, as a mask; removal of said photoresist pattern, and of said polymer spacers; ion implanting a first conductivity imparting dopant, into an area of said semiconductor substrate, exposed in said narrow hole opening in said first dielectric layer, to create said local threshold adjust region; growing a gate insulator layer on said semiconductor substrate, exposed in said narrow hole opening in said first dielectric layer; depositing a polysilicon layer, completely filling said narrow hole opening in said first dielectric layer; planarization of said polysilicon layer, by removal of said polysilicon layer from top surface of said first dielectric layer, forming a polysilicon gate structure in said narrow hole opening in said first dielectric layer; removal of a top portion of said first dielectric layer; complete removal of said first dielectric layer, exposing all surfaces of said polysilicon gate structure; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to form a lightly doped source and drain region; depositing a first insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said first insulator layer, to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a second insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said second insulator layer, to expose top surface of said heavily doped source and drain region, and to expose top surface of said polysilicon gate structure; depositing a metal layer on top surface of said second insulator layer, on top surface of said heavily doped source and drain region, and on top surface of said polysilicon gate structure, exposed in said contact hole; and patterning of said metal layer, to form metal contact structures to said heavily doped source and drain region, and to said polysilicon gate structure.

Claim 12

A method of fabricating a deep, submicron MOSFET device, on a semiconductor substrate, with a local threshold voltage adjust region, self aligned to a polysilicon gate structure, comprising the steps of: depositing a first silicon oxide dielectric layer on said semiconductor substrate layer; forming a photoresist pattern, in a photoresist layer, on said first dielectric layer, with a deep submicron opening in said photoresist layer, exposing top surface of said first dielectric layer; forming polymer spacers on the sides of said deep submicron opening, in said photoresist layer, creating a polymer coated opening, in said photoresist layer; forming a deep submicron hole opening in said first dielectric layer, by etching of said first dielectric layer, exposed in said polymer coated opening, in said photoresist layer, as a mask; removal of said photoresist pattern, and of said polymer spacers; ion implanting a first conductivity imparting dopant into an area of said semiconductor substrate exposed in said deep submicron hole opening, in said first dielectric layer, to create said local threshold voltage adjust region; growing a gate insulator layer on said semiconductor substrate, exposed in said deep submicron hole opening, in said first dielectric layer; depositing a first polysilicon layer, completely filling said deep submicron hole opening in said first dielectric layer; planarization of said first polysilicon layer, by removal of said first polysilicon layer from top surface of said first dielectric layer, to form said polysilicon gate structure, in said deep submicron hole opening in said first dielectric layer, and self aligned to said local threshold voltage adjust region; removal of a top portion of said first dielectric layer; complete removal of said first dielectric layer, exposing all surfaces of said polysilicon gate structure; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to form a lightly doped source and drain region; depositing a first insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said first insulator layer to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a second insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said second insulator layer, to expose top surface of said heavily doped source and drain regions, and to expose top surface of said polysilicon gate structure; depositing a metal layer on the top surface of said second insulator layer, on the top surface of said heavily doped source and drain region, and on top surface of said polysilicon gate structure, exposed in said contact hole; and patterning of said metal layer to form metal contact structures to said heavily doped source and drain region, and to said polysilicon gate structure.

Claim 13

A method of fabricating a deep, submicron MOSFET device, on a semiconductor substrate, with a local threshold voltage adjust region, self aligned to a polysilicon gate structure, comprising the steps of: depositing a first silicon oxide dielectric layer on said semiconductor substrate layer; forming a photoresist pattern, in a photoresist layer, on said first dielectric layer, with a deep submicron opening in said photoresist layer, exposing top surface of said first dielectric layer; forming polymer spacers on the sides of said deep submicron opening, in said photoresist layer, creating a polymer coated opening, in said photoresist layer; forming a deep submicron hole opening in said first dielectric layer, by etching of said first dielectric layer, exposed in said polymer coated opening, in said photoresist layer, as a mask; removal of said photoresist pattern, and of said polymer spacers; ion implanting a first conductivity imparting dopant into an area of said semiconductor substrate exposed in said deep submicron hole opening, in said first dielectric layer, to create said local threshold voltage adjust region; growing a gate insulator layer on said semiconductor substrate, exposed in said deep submicron hole opening, in said first dielectric layer; depositing a first polysilicon layer, completely filling said deep submicron hole opening in said first dielectric layer; planarization of said first polysilicon layer, by removal of said first polysilicon layer from top surface of said first dielectric layer, to form said polysilicon gate structure, in said deep submicron hole opening in said first dielectric layer, and self aligned to said local threshold voltage adjust region; removal of a top portion of said first dielectric layer; complete removal of said first dielectric layer, exposing all surfaces of said polysilicon gate structure; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to form a lightly doped source and drain region; depositing a first insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said first insulator layer to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a second insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said second insulator layer, to expose top surface of said heavily doped source and drain regions, and to expose top surface of said polysilicon gate structure; depositing a metal layer on the top surface of said second insulator layer, on the top surface of said heavily doped source and drain region, and on top surface of said polysilicon gate structure, exposed in said contact hole; and patterning of said metal layer to form metal contact structures to said heavily doped source and drain region, and to said polysilicon gate structure.