Spin-on-glass partial etchback planarization process

Claim 1

The method of planarizing the dielectric layers between conductive layers in integrated circuits without the incorporation of voids in said dielectric layers comprising: providing device structures in and on a semiconductor substrate; providing at least one patterned conductive layer having spaced conductive lines for contacting of said device structures; said spaced conductive lines and the surface of said substrate present a non-planar top surface having valleys between said spaced conductive lines; forming a first dielectric layer over said non-planar top surface whereby closed cavities are formed between said spaced conductive lines; covering said first dielectric layer with a first spin-on-glass layer; anisotropically etching said first spin-on-glass layer and said first dielectric layer to a depth which exposes said closed cavities and forms open hollows, wherein said etching continues to a depth which does not expose said spaced conductive lines; covering the remaining first spin-on-glass layer with a second spin-on-glass layer whereby said open hollows are filled with said second spin-on-glass layer; curing both said first and second spin-on-glass layers; anisotropically etching at least said second spin-on-glass layer to expose at least portions of the first dielectric layer over said spaced conductive lines; depositing a second dielectric layer over said first and second spin-on-glass layers to complete said planarization; anisotropically etching via holes in selected locations through said first and second dielectric layers to expose said spaced conductive lines; and forming metal contacts through said via holes to contact said conductive lines.

Claim 2

The method of planarizing the dielectric layers between conductive layers in integrated circuits without the incorporation of voids in said dielectric layers comprising: providing device structures in and on a semiconductor substrate; providing at least one patterned conductive layer having spaced conductive lines for contacting of said device structures; said spaced conductive lines and the surface of said substrate present a non-planar top surface having valleys between said spaced conductive lines; forming a first dielectric layer over said non-planar top surface whereby closed cavities are formed between said spaced conductive lines; covering said first dielectric layer with a first spin-on-glass layer; anisotropically etching said first spin-on-glass layer and said first dielectric layer to a depth which exposes said closed cavities and forms open hollows, wherein said etching continues to a depth which does not expose said spaced conductive lines; covering the remaining first spin-on-glass layer with a second spin-on-glass layer whereby said open hollows are filled with said second spin-on-glass layer; curing both said first and second spin-on-glass layers; anisotropically etching at least said second spin-on-glass layer to expose at least portions of the first dielectric layer over said spaced conductive lines; depositing a second dielectric layer over said first and second spin-on-glass layers to complete said planarization; anisotropically etching via holes in selected locations through said first and second dielectric layers to expose said spaced conductive lines; and forming metal contacts through said via holes to contact said conductive lines.

Claim 17

The method of planarizing the dielectric layers between conductor layers in integrated circuits without the incorporation of voids in said dielectric layers comprising: providing device structures in and on a semiconductor substrate; providing at least one patterned conductive layer having spaced conductive lines for contacting of said device structures; said spaced conductive lines and the surface of said substrate present a non-planar top surface having valleys between said spaced conductive lines; the distance between said spaced conductive lines is in a range of about 3000 to 10,000 Å; forming a first dielectric layer over said non-planar top surface whereby closed cavities are formed between said spaced conductive lines; said first dielectric layer has a thickness greater than one half of the distance between said spaced conductive lines; said first dielectric layer has a thickness in a range of about 3000 to 10,000 Å; covering said first dielectric layer with a first spin-on-glass layer; said first spin-on-glass layer having a thickness in a range of between about 1000 and 7000 Å; anisotropically etching said first spin-on-glass layer and said first insulator layer to a depth which exposes said closed cavities and forming open hollows, wherein said etching continues to a depth which does not expose said spaced conductive lines; covering the remaining first spin-on-glass layer with a second spin-on-glass layer whereby said open hollows are filled with said second spin-on-glass layer, said second spin-on-glass layer has a thickness of between about 1000 and 6000 Å; curing both said first and second spin-on-glass layers; anisotropically etching at least said second spin-on-glass layer to expose at least portions of the first dielectric layer over the spaced conductive lines; and depositing a second dielectric layer over said first and second spin-on-glass layers to complete said planarization, said second dielectric layer having a thickness in a range of between about 2000 and 6000 Å; anisotropically etching via holes in selected locations through said first and second dielectric layers to expose said spaced conductive lines; and forming metal contacts through said via holes to contact said conductive lines.

Claim 18

The method of planarizing the dielectric layers between conductor layers in integrated circuits without the incorporation of voids in said dielectric layers comprising: providing device structures in and on a semiconductor substrate; providing at least one patterned conductive layer having spaced conductive lines for contacting of said device structures; said spaced conductive lines and the surface of said substrate present a non-planar top surface having valleys between said spaced conductive lines; the distance between said spaced conductive lines is in a range of about 3000 to 10,000 Å; forming a first dielectric layer over said non-planar top surface whereby closed cavities are formed between said spaced conductive lines; said first dielectric layer has a thickness greater than one half of the distance between said spaced conductive lines; said first dielectric layer has a thickness in a range of about 3000 to 10,000 Å; covering said first dielectric layer with a first spin-on-glass layer; said first spin-on-glass layer having a thickness in a range of between about 1000 and 7000 Å; anisotropically etching said first spin-on-glass layer and said first insulator layer to a depth which exposes said closed cavities and forming open hollows, wherein said etching continues to a depth which does not expose said spaced conductive lines; covering the remaining first spin-on-glass layer with a second spin-on-glass layer whereby said open hollows are filled with said second spin-on-glass layer, said second spin-on-glass layer has a thickness of between about 1000 and 6000 Å; curing both said first and second spin-on-glass layers; anisotropically etching at least said second spin-on-glass layer to expose at least portions of the first dielectric layer over the spaced conductive lines; and depositing a second dielectric layer over said first and second spin-on-glass layers to complete said planarization, said second dielectric layer having a thickness in a range of between about 2000 and 6000 Å; anisotropically etching via holes in selected locations through said first and second dielectric layers to expose said spaced conductive lines; and forming metal contacts through said via holes to contact said conductive lines.

Claim 26

A method of planarizing the dielectric layers between conductor layers in integrated circuits without the incorporation of closed cavities in said dielectric layers comprising: providing device structures in and on a semiconductor substrate; providing at least one patterned conductive layer having spaced conductive lines for contacting of said device structures; said spaced conductive lines and the surface of said substrate present a non-planar top surface having valleys between said spaced conductive lines; the distance between said spaced conductive lines is in a range of between about 0.3 and 1.0 μm; forming a first dielectric layer over said non-planar top surface whereby closed cavities can be formed between said spaced conductive lines; said first dielectric layer has a thickness greater than one half of the distance between said spaced conductive lines, said first dielectric layer is composed of silicon oxide formed by a plasma enhanced chemical vapor deposition process; said first dielectric layer has a thickness in the range of about 3000 to 10,000 Å; covering said first dielectric layer with a first spin-on-glass layer; said first spin-on-glass layer composed of siloxane; curing said first spin-on-glass layer; anisotropically etching said first spin-on-glass layer and said first insulator layer to a depth which exposes said closed cavities and forming open voids, wherein said etching continues to a depth which does not expose said spaced conductive lines; the anisotropic etch back of said first spin-on-glass layer has the conditions of about: a CHF 3 flow of between about 27 and 33 sccms, a CF 4 flow between about 45 to 55 sccm, a Pressure between about 270 to 330 mtorr, and a Power between about 450 to 550 watts; covering the remaining first spin-on-glass layer with a second spin-on-glass layer whereby said open hollows are filled with said second spin-on-glass layer, said second spin-on-glass layer has a thickness of between about 1000 and 6000 Å; curing both said first and second spin-on-glass layers; anisotropically etching at least said second spin-on-glass layer to expose at least portions of the first dielectric layer over the spaced conductive lines; and depositing a second dielectric layer over said first and second spin-on-glass layers to complete said planarization, said second dielectric layer having a thickness of between about 2000 to 6000 Å and is formed by a plasma enhanced chemical vapor deposition process; anisotropically etching via holes in selected locations through said first and second dielectric layers to expose said spaced conductive lines; and forming metal contacts through said via holes to contact said conductive lines.

Claim 27

A method of planarizing the dielectric layers between conductor layers in integrated circuits without the incorporation of closed cavities in said dielectric layers comprising: providing device structures in and on a semiconductor substrate; providing at least one patterned conductive layer having spaced conductive lines for contacting of said device structures; said spaced conductive lines and the surface of said substrate present a non-planar top surface having valleys between said spaced conductive lines; the distance between said spaced conductive lines is in a range of between about 0.3 and 1.0 μm; forming a first dielectric layer over said non-planar top surface whereby closed cavities can be formed between said spaced conductive lines; said first dielectric layer has a thickness greater than one half of the distance between said spaced conductive lines, said first dielectric layer is composed of silicon oxide formed by a plasma enhanced chemical vapor deposition process; said first dielectric layer has a thickness in the range of about 3000 to 10,000 Å; covering said first dielectric layer with a first spin-on-glass layer; said first spin-on-glass layer composed of siloxane; curing said first spin-on-glass layer; anisotropically etching said first spin-on-glass layer and said first insulator layer to a depth which exposes said closed cavities and forming open voids, wherein said etching continues to a depth which does not expose said spaced conductive lines; the anisotropic etch back of said first spin-on-glass layer has the conditions of about: a CHF 3 flow of between about 27 and 33 sccms, a CF 4 flow between about 45 to 55 sccm, a Pressure between about 270 to 330 mtorr, and a Power between about 450 to 550 watts; covering the remaining first spin-on-glass layer with a second spin-on-glass layer whereby said open hollows are filled with said second spin-on-glass layer, said second spin-on-glass layer has a thickness of between about 1000 and 6000 Å; curing both said first and second spin-on-glass layers; anisotropically etching at least said second spin-on-glass layer to expose at least portions of the first dielectric layer over the spaced conductive lines; and depositing a second dielectric layer over said first and second spin-on-glass layers to complete said planarization, said second dielectric layer having a thickness of between about 2000 to 6000 Å and is formed by a plasma enhanced chemical vapor deposition process; anisotropically etching via holes in selected locations through said first and second dielectric layers to expose said spaced conductive lines; and forming metal contacts through said via holes to contact said conductive lines.