US5472825A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Metal interconnect fabrication with dual plasma silicon dioxide deposition and etchback
Assignee: Philips Semiconductors Inc
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Filing: 1993-09-24
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Granted: 1995-12-05
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Expires: 2013-09-24
Abstract
Abstract In the fabrication of an integrated circuit, an intermetal dielectric is formed using a plural plasma processes that can be performed without having to transfer the wafer in the interim. This saves on wafer handling. A wafer with a patterned first metal wafer is placed into a plasma chamber. A relatively low-power noble gas plasma is applied to clean the wafer. A reactive plasma treatment is then used to deposit silicon dioxide to a thickness greater than ultimately desired. A noble gas plasma is used to etch back the silicon dioxide. Spin-on glass is then applied. The previous etch back aids the conformance of the spin-on glass to the underlying structure. The spin-on glass can be polished for further planarization. A second silicon dioxide layer can be deposited on top of the spin-on glass. Via apertures can be photolithographically defined through the three-layer dielectric. Finally, second layer metal is deposited and patterned. The method provides for high wafer throughput, while minimizing voids at the interface between the spin-on glass and the underlying silicon dioxide layer.
Inventors
- 👤 Anthony Sayka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:16
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10W20/074; H10W20/077; H10W20/081; H10W20/083; H10W20/092; H10W20/40; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
117 words
A method for forming a metal interconnect structure for an integrated circuit, said method comprising the steps of: fabricating an integrated circuit up to and including a substep of patterning a first metal; introducing said integrated circuit into a plasma chamber; introducing oxygen-bearing gas into said chamber; ionizing said oxygen-bearing gas so that silicon dioxide is deposited on said integrated circuit; introducing noble gas into said chamber; ionizing said noble gas so that said silicon dioxide is etched back; removing said integrated circuit from said plasma chamber; applying spin-on glass to said integrated circuit; depositing silicon dioxide on said spin-on glass; photolithographically defining vias to said first metal; depositing a second metal; and patterning said second metal.
Claim 2
Independent Claim
117 words
A method for forming a metal interconnect structure for an integrated circuit, said method comprising the steps of: fabricating an integrated circuit up to and including a substep of patterning a first metal; introducing said integrated circuit into a plasma chamber; introducing oxygen-bearing gas into said chamber; ionizing said oxygen-bearing gas so that silicon dioxide is deposited on said integrated circuit; introducing noble gas into said chamber; ionizing said noble gas so that said silicon dioxide is etched back; removing said integrated circuit from said plasma chamber; applying spin-on glass to said integrated circuit; depositing silicon dioxide on said spin-on glass; photolithographically defining vias to said first metal; depositing a second metal; and patterning said second metal.
Claim 3
Dependent Claim
30 words
A method as recited in claim 1 further comprising polishing said integrated circuit after said spin-on glass is applied and before said silicon dioxide is deposited on said spin-on glass.
Claim 4
Dependent Claim
35 words
A method as recited in claim 1 wherein, in said step of ionizing said noble gas, radio frequency energy characterized by a power between 150 watts and 250 watts is used to effect the ionization.
Claim 5
Dependent Claim
29 words
A method as recited in claim 3 wherein, in said step of ionizing said noble gas, said plasma chamber is under a pressure between 0.1 Torr and 0.2 Torr.
Claim 6
Independent Claim
147 words
A method for forming a metal interconnect structure for an integrated circuit, said method comprising the steps of: fabricating an integrated circuit through patterning a first metal; introducing said integrated circuit into a plasma chamber; introducing reactant gases into said chamber; ionizing said reactant gases at an rf power of 150-300 watts and a pressure of less than 3 Torr so that silicon dioxide is deposited on said integrated circuit; introducing noble gas into said chamber; ionizing said noble gas at an rf power of 150 to 250 watts and a pressure of 0.1 to 0.2 Torr so that said silicon dioxide is etched back; removing said integrated circuit from said plasma chamber; applying spin-on glass on said integrated circuit; polymerizing said spin-on glass; depositing silicon dioxide on said spin-on glass; photolithographically defining vias to said first metal; depositing a second metal; and patterning said second metal.
Claim 7
Independent Claim
147 words
A method for forming a metal interconnect structure for an integrated circuit, said method comprising the steps of: fabricating an integrated circuit through patterning a first metal; introducing said integrated circuit into a plasma chamber; introducing reactant gases into said chamber; ionizing said reactant gases at an rf power of 150-300 watts and a pressure of less than 3 Torr so that silicon dioxide is deposited on said integrated circuit; introducing noble gas into said chamber; ionizing said noble gas at an rf power of 150 to 250 watts and a pressure of 0.1 to 0.2 Torr so that said silicon dioxide is etched back; removing said integrated circuit from said plasma chamber; applying spin-on glass on said integrated circuit; polymerizing said spin-on glass; depositing silicon dioxide on said spin-on glass; photolithographically defining vias to said first metal; depositing a second metal; and patterning said second metal.
References Cited (Backward Citations)
US4176003A
Cited
US5310621A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |