Method and apparatus for inputting data to a single instruction, multiple data processor used in a television receiving system

Claim 1

A television receiving system for processing a video signal, comprising: an analog to digital converter for converting said video signal into data samples having B bits, where B is a number greater than one; a single-instruction multiple-dam processor having a plurality of computational elements in near-neighbor communication with each other, and having a data input register; said data input register further comprising: an array of R rows by C columns of memory cells, where each column of said memory cells is an input element; said array being partially populated such that each column contains only B of said memory cells, where B is less than R; a first port connected to said converter for receiving said data samples by transferring in a single transaction a first data word comprising a set of N of said data samples, where N is a number greater than one, to N of said input elements, such that one of each of said set of data samples is transferred to a corresponding one of said N input elements; a second port for transferring said data samples to said processor having each of said input elements connected to a corresponding computational element, such that a second data word having at least a portion of each of said data samples stored in C of said input elements is transferred in a single transaction to said corresponding computational elements, a control circuit in communication with said data input register; a processor control unit connected to said control circuit for generating control and timing signals for use by said control circuit; an instruction generator connected to said single-instruction multiple-data processor for generating instructions for simultaneous use by each computational element of said single-instruction multiple-data processor, said computational elements of said single-instruction multiple-dam processor thereby producing processed data samples; a digital to analog converter connected to said single-instruction multiple-data processor for converting said processed data samples to an analog signal for display; and a display connected to said analog to digital converter for displaying pixels corresponding to said analog signal.

Claim 8

A method of receiving data samples into a single-instruction multiple-data processor having a data input register with input elements for storing said data samples, each of said elements connected to a corresponding computational element of said processor, where each data sample has B bits, and B is a number greater than one said method comprising the steps of: providing said data input register with an array of R rows by C columns of memory cells, where R and C are each numbers greater than one, such that each of said input elements is a column of said memory cells; said array being partially populated such that each column contains only B of said memory cells, where B is less than R; providing a word comprised of a set of N data samples on a corresponding number of data channels to said data input register; providing a write enable signal to a set of N input elements of said data input register during a single write cycle; controlling said write enable signal such that a different one of said set of N data samples is written to each said input element in said set of N input elements in a single write cycle; and transferring a second data word from said input register to said processor such that said second data word is comprised of at least one bit of each of said input elements.

Claim 9

A method of receiving data samples into a single-instruction multiple-data processor having a data input register with input elements for storing said data samples, each of said elements connected to a corresponding computational element of said processor, where each data sample has B bits, and B is a number greater than one said method comprising the steps of: providing said data input register with an array of R rows by C columns of memory cells, where R and C are each numbers greater than one, such that each of said input elements is a column of said memory cells; said array being partially populated such that each column contains only B of said memory cells, where B is less than R; providing a word comprised of a set of N data samples on a corresponding number of data channels to said data input register; providing a write enable signal to a set of N input elements of said data input register during a single write cycle; controlling said write enable signal such that a different one of said set of N data samples is written to each said input element in said set of N input elements in a single write cycle; and transferring a second data word from said input register to said processor such that said second data word is comprised of at least one bit of each of said input elements.