Pixel slice processor with frame buffers grouped according to pixel bit width

Claim 1

A graphic processor for single instruction multiple data operations on k pixels simultaneously, each pixel having at most n bits, where k and n are integers each greater than one, which processor is also easily expandable in terms of pixel length and can efficiently handle conditional operations requiring efficient interpixel communications comprising: a plurality of n frame buffers, each buffer storing data of k bit width, said plurality of frame buffers arranged in groups of i frame buffers per group, where n and i are each integers greater than one and i is an integer less than n to provide n/i groups of frame buffers, a plurality of pixel slice processors, each operating on data of i bit width, said plurality of pixel slice processors arranged in n/i groups of k processors per group where each frame buffer group has a corresponding pixel slice processor group, data path means to provide for: (i) bidirectional, bit-parallel data flow within a group between said frame buffers and said pixel slice processors, (ii) data flow between pixel slice processors of a group, and (iii) data flow between corresponding pixel slice processors of different groups, said data path means providing bidirectional, bit parallel data flow within a group including connections between each pixel slice processor and each frame buffer where each frame buffer of a group is connected only to pixel slice processors of that group, whereby computations requiring intra pixel carries and conditional computations requiring inter pixel communications are provided for on said data path means and extensions of pixel length are handled by increases in the integer n.