Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
168 words
Data processing apparatus comprising: (a) a plurality of integrated circuit chips each comprising a plurality of data processing elements, (b) means for connecting said processing elements on all the chips together to form an array of rows and columns, allowing transfer of data between adjacent elements in each row and column, (c) first switching logic means within each chip for subdividing each row/column into a first plurality of sections, all said processing elements in each individual section being on the same chip, and for interconnecting first and last processing elements in each said section to allow data to be shifted cyclically through said processing elements in that section, and (d) second switching logic means external to the chips for subdividing each row/column into a second plurality of sections, each of which contains processing elements from at least two different ones of said chips, and for interconnecting first and last processing elements in each section to allow data to be shifted cyclically through said processing elements in that section.
Claim 2
Dependent Claim
168 words
Data processing apparatus comprising: (a) a plurality of integrated circuit chips each comprising a plurality of data processing elements, (b) means for connecting said processing elements on all the chips together to form an array of rows and columns, allowing transfer of data between adjacent elements in each row and column, (c) first switching logic means within each chip for subdividing each row/column into a first plurality of sections, all said processing elements in each individual section being on the same chip, and for interconnecting first and last processing elements in each said section to allow data to be shifted cyclically through said processing elements in that section, and (d) second switching logic means external to the chips for subdividing each row/column into a second plurality of sections, each of which contains processing elements from at least two different ones of said chips, and for interconnecting first and last processing elements in each section to allow data to be shifted cyclically through said processing elements in that section.
Claim 3
Dependent Claim
47 words
Apparatus according to claim 1 wherein the first switching logic means comprises means for shifting data between sad processing elements by way of parallel data paths, and the second switching logic means comprises means for shifting data between said processing elements by way of serial data paths.
Claim 4
Dependent Claim
40 words
Apparatus according to claim 2 wherein each processing element comprises a shift register having a parallel output connected to respective one of said parallel data paths and a serial output connected to a respective one of said serial data paths.
Claim 5
Dependent Claim
74 words
Apparatus according to claim 3 wherein each processing element includes a local memory having a parallel data output, and a multiplexer having: (a) an output connected to a parallel input of said shift register, (b) a first input connected to the parallel data output of the local memory, and (c) a plurality of further inputs connected to the parallel data outputs of the shift registers in the other processing elements in the same chip.
Claim 6
Dependent Claim
63 words
Apparatus according to claim 3 wherein each processing element comprises a multiplexer having: (a) an output connected to a serial input of said shift register, (b) a first input connected to a respective one of said serial data paths, and (c) a plurality of further inputs connected to the serial data outputs of the shift registers in neighbouring processing elements in the array.