Multiphase logic circuit

Claim 2

A logic circuit comprising: an input node; an output node; first gate means; second gate means; said second gate means including first precharge means for setting said output node to a first voltage level; said second gate means further including first logic means for selectively discharging said output node to a second voltage level in response to first input logic signal levels at said input node, said first logic means having a control electrode connected to said input node; second logic means connected in parallel with said first logic means for selectively dicharging said output node; said first gate means connected to said control electrode of said first logic means for disabling said first logic means; said second gate means connecting said second logic means to said output node; and a common input control line connected to said first and said second gate means for controlling the operation thereof.

Claim 3

The logic circuit of claim 1 wherein said first and second gate means include, respectively, first and second gating devices enabled by control signals supplied to a control electrode thereof from said common control line, said first gate means, when enabled, supplying a potential to the control electrode of said first logic means to prevent discharge of said output node by said first logic means, whereby said second logic means control the selective discharge of said output node without interference from said first logic means.

Claim 4

The logic circuit of claim 2 further including: means for supplying said control signals to the control electrodes of said first and second gating devices during a first portion of an operating cycle; a third gating device for discharging said output node, said third gating device being enabled by a signal supplied to a control electrode thereof; and means for supplying the signal to said control electrode of said third gating device during a second portion of said operating cycle.

Claim 5

The logic circuit of claim 3 further including; an output gating circuit operative during said second portion of said operating cycle; isolation means for connecting said output node to said output gating circuit during said first portion of said operating cycle to supply the output voltage signal established by the selective discharge of said output node to said output gating circuit; and an output control line connected to said output gating circuit for controlling operation thereof.

Claim 6

The logic circuit of claim 4 wherein said output control line is connected to said control electrode of said third gating device.

Claim 7

The logic circuit of claim 1, wherein said first gate means includes: second precharge means for setting said input node to said first voltage level; third logic means adapted to selectively discharge said input node to said second voltage level in response to second input logic signal levels applied to a control electrode of said third logic means; said second precharge means and said third logic means electrically connected in parallel with respect to one another between a common terminal thereof and a source of reference voltage; means for connecting said source of reference voltage to a control electrode of said second precharge means.

Claim 8

The logic circuit of claim 6, further including isolation means connecting said third logic means to said input node during said second portion of said operating cycle.

Claim 9

The logic circuit of claim 6, wherein said first, second and third logic means and said first and second precharge means are p-channel insulated gate field effect transistors.

Claim 10

In combination: a shift register comprising a plurality of register cells, each cell adapted to store a bit of binary data; means connecting said register cells in serial fashion for propagating the stored bits of binary data serially through the register; input gate means for loading binary data into respective cells of the register; output gate means connected to respective cells of the register for transferring binary data in parallel from the register; and discharge means for clearing said binary data from said register cells in order to prevent the serial propagation thereof.

Claim 11

In combination: a shift register comprising a plurality of register cells, each cell adapted to store a bit of binary data; means connecting said register cells in serial fashion for propagating the stored bits of binary data serially through the register; input gate means for loading binary data into respective cells of the register; output gate means connected to respective cells of the register for transferring binary data in parallel from the register; and discharge means for clearing said binary data from said register cells in order to prevent the serial propagation thereof.

Claim 12

The combination of claim 9 further including; a common control line connected to said output gate means and to said discharge means for controlling operation thereof, whereby said stored binary data is cleared by said discharge means to prevent serial propagation thereof during said parallel data transfer.

Claim 13

The combination of claim 10 wherein each of said register cells includes a logic gate having input and output nodes and a first logic network for setting the output voltage level at said output node in response to input voltage levels at said input node; said input gate means includes first gate means connected to said input node for clamping said inpUt node to a given voltage level for disabling said first logic network and second gate means for connecting a second logic network to said output node for setting the output voltage level thereat without interference from said first logic network; and a common line connected to said first and said second gate means for controlling the operation thereof.

Claim 14

A ratioless logic circuit comprising: an input terminal; an output terminal; a source of first and second reference voltages; precharge means for setting said output terminal to said first reference voltage, a control electrode thereof connected to said source of reference voltages; isolation means adapted to connect said precharge means to said output terminal during a first portion of an operating cycle; gating means connected to said output terminal and adapted to discharge said output terminal to said second reference voltage in response to a control signal applied to a control electrode thereof; logic means having a control electrode thereof connected said input terminal and adapted to discharge said output terminal to said second reference voltage in response to an input logic level signal applied to said input terminal; said precharge means and said logic means electrically connected in parallel with respect to each other between a common terminal thereof and said source of reference voltages, and means for supplying said control signal to said gating means control electrode during a second portion of said operating cycle to thereby enable said gating means and discharge said output node.

Claim 15

A ratioless logic circuit comprising: an input terminal; an output terminal; a source of first and second reference voltages; precharge means for setting said output terminal to said first reference voltage, a control electrode thereof connected to said source of reference voltages; isolation means adapted to connect said precharge means to said output terminal during a first portion of an operating cycle; gating means connected to said output terminal and adapted to discharge said output terminal to said second reference voltage in response to a control signal applied to a control electrode thereof; logic means having a control electrode thereof connected said input terminal and adapted to discharge said output terminal to said second reference voltage in response to an input logic level signal applied to said input terminal; said precharge means and said logic means electrically connected in parallel with respect to each other between a common terminal thereof and said source of reference voltages, and means for supplying said control signal to said gating means control electrode during a second portion of said operating cycle to thereby enable said gating means and discharge said output node.