US4727474A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Staging memory for massively parallel processor
Assignee: Lockheed Martin Tactical Systems Inc
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Filing: 1983-02-18
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Granted: 1988-02-23
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Expires: 2003-02-18
Abstract
Abstract The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.
Inventors
- 👤 Kenneth E. Batcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:36
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
179 words
A computer organization, comprising: a host computer; a program and data management unit; a processing array unit; an array control unit interconnected among said host computer, program and data management unit, and processing array unit; and a staging memory interconnected between said host computer, program and data management unit, and processing array unit, said staging memory comprising: input means connected to said host computer, program and data management unit, and said processing array unit for receiving data therefrom; output means connected to said host computer, program and data management unit, and said processing array unit for passing data thereto; and a main stager interposed between said input and output means for receiving and maintaining large volumes of data therein, said main stager including a plurality of memory banks for receiving and maintaining data, said banks receiving and transferring data in parallel, said memory banks being connected in parallel to addressing means for accessing storage locations in said memory banks and wherein a memory bank L stores words whose addresses are congruent to L modulo the number of memory banks.
Claim 2
Dependent Claim
179 words
A computer organization, comprising: a host computer; a program and data management unit; a processing array unit; an array control unit interconnected among said host computer, program and data management unit, and processing array unit; and a staging memory interconnected between said host computer, program and data management unit, and processing array unit, said staging memory comprising: input means connected to said host computer, program and data management unit, and said processing array unit for receiving data therefrom; output means connected to said host computer, program and data management unit, and said processing array unit for passing data thereto; and a main stager interposed between said input and output means for receiving and maintaining large volumes of data therein, said main stager including a plurality of memory banks for receiving and maintaining data, said banks receiving and transferring data in parallel, said memory banks being connected in parallel to addressing means for accessing storage locations in said memory banks and wherein a memory bank L stores words whose addresses are congruent to L modulo the number of memory banks.
Claim 3
Dependent Claim
20 words
The computer organization according to claim 1 wherein said plurality of memory banks is a number evenly divisible by four.
Claim 4
Dependent Claim
28 words
The computer organization according to claim 1 wherein said addressing means includes a code generating means for mutually exclusively accessing a word in each of said memory banks.
Claim 5
Dependent Claim
65 words
The computer organization according to claim 3 wherein said main stager further includes an input permutation network and an output permutation network respectively connected to said input and said output means, said input permutation network routing input data words to the memory banks containing a corresponding word address, and said output permutation network routing output data words from said memory banks to said output means.
Claim 6
Dependent Claim
30 words
The computer organization according to claim 4 wherein said input means includes an input port for shuffling input data prior to passage of said data to said input permutation network.
Claim 7
Dependent Claim
30 words
The computer organization according to claim 5 wherein said output means includes an output port for shuffling output data prior to passage of said data to said output permutation network.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-22 | 1991-08-24 | 1992-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-22 | 1995-08-24 | 1996-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-22 | 1999-08-24 | 2000-02-23 | $7700.00 | Window Closed / Lapsed |