§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
US3812467A Expired / Lapsed US ⏱️ 0.0 years remaining

Permutation network

Assignee: Lockheed Martin Tactical Systems Inc
•
Filing: 1972-09-25
•
Granted: 1974-05-21
•
Expires: 1992-09-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The instant invention relates to a unique logic network whereby data into and out of the memory array of a specialized digital computer will be permuted such that the data will maintain a convenient and consistent order on a data interface. The network may be constructed using commonly-available n-channel data selectors. Fundamentally, the invention functions in conjunction with a digital computer memory array whose data storage pattern is such that accesses to the stored data may be made in wordoriented mode, bit-oriented mode, or mixed-oriented mode, the latter comprising characteristics of the two aforementioned modes. The invention requires a minimum amount of extra-network control circuitry, and comprises a plurality of uniquely identical smaller networks of such size that they may be readily packaged on individual printed circuit boards such that a minimum of interboard wire connections are necessary. Further, the similarity of smaller networks facilitates maintainability of the entire network.

Inventors

  • 👤 K Batcher

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 02:02
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/762; G06F12/00; G06F12/02; G06F12/0207; G06F5/00; G06F5/01; G06F5/015

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 150 words
A network of logic circuitry for permuting the lineal order of data from 2n data sources each designated by an n-element binary vector index M, unique for each source, to 2n data positions each designated by an n-element binary vector P, unique for each data position, in accordance with the state or a permutation code designated by an n-element binary vector X such that the permuted data position P of the data from any data source M is given by P M + X, where + means addition modulo 2 and where n is an integer greater than 1, comprising: a plurality of k-channel data selectors having channel select input lines and arranged in r levels, 0 through (r-1), of 2n data selectors each, wherein k has the same value, kz, for all data selectors within a given level z but may have different values for each level such that
Claim 2
Dependent Claim 150 words
A network of logic circuitry for permuting the lineal order of data from 2n data sources each designated by an n-element binary vector index M, unique for each source, to 2n data positions each designated by an n-element binary vector P, unique for each data position, in accordance with the state or a permutation code designated by an n-element binary vector X such that the permuted data position P of the data from any data source M is given by P M + X, where + means addition modulo 2 and where n is an integer greater than 1, comprising: a plurality of k-channel data selectors having channel select input lines and arranged in r levels, 0 through (r-1), of 2n data selectors each, wherein k has the same value, kz, for all data selectors within a given level z but may have different values for each level such that
Claim 3
Dependent Claim 36 words
The network of logic circuitry as recited in claim 1 wherein the k-channel data selectors are identical for all levels, the network comprising r2n k-channel data selectors arranged in r levels of 2n data selectors each.
Claim 4
Dependent Claim 20 words
The network of logic circuitry as recited in claim 1 wherein the circuit means comprises an n-bit binary data register.
Claim 5
Dependent Claim 33 words
The network of logic circuitry as recited in claim 1 wherein the corresponding channel select input lines of the data selectors within each level are connected parallel to corresponding output of the register.
Claim 6
Dependent Claim 31 words
The network of logic circuitry as recited in claim 1 wherein the number of functionally distinct connections made between the circuit means and the channel select input lines is equivalent to

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-05-20 1977-11-19 1978-05-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-05-20 1981-11-19 1982-05-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-05-20 1985-11-19 1986-05-21 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag