US5654917A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for making and programming a flash memory array
Assignee: International Business Machines Corp
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Filing: 1996-05-14
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Granted: 1997-08-05
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Expires: 2016-05-14
Abstract
Abstract A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells. Programming may be implemented with channel hot-electron tunneling using relatively low programming voltages thereby realizing faster programming time and closer bit-line spacing.
Inventors
- 👤 Seiki Ogura
- 👤 Nivo Rovedo
- 👤 Robert C. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:07
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/972
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
136 words
A process for writing a word of data to an array having N-bit lines and M-word lines comprising the steps of: a) applying a first voltage potential to each of N-bit lines; b) determining if the writing process is to start at the least significant bit line or at an Nth bit-line; c) applying a second voltage potential to said least significant bit-line if it is determined in step (b) that said writing process shall begin at said least significant bit-line and thereafter sequentially applying the second voltage potential to each succeeding bit line; and d) applying the second voltage potential to the Nth bit-line if it is determined in step (b) that said writing process shall start at the Nth bit-line and thereafter sequentially applying the second voltage potential to each bit-line in descending order.
Claim 2
Dependent Claim
136 words
A process for writing a word of data to an array having N-bit lines and M-word lines comprising the steps of: a) applying a first voltage potential to each of N-bit lines; b) determining if the writing process is to start at the least significant bit line or at an Nth bit-line; c) applying a second voltage potential to said least significant bit-line if it is determined in step (b) that said writing process shall begin at said least significant bit-line and thereafter sequentially applying the second voltage potential to each succeeding bit line; and d) applying the second voltage potential to the Nth bit-line if it is determined in step (b) that said writing process shall start at the Nth bit-line and thereafter sequentially applying the second voltage potential to each bit-line in descending order.
Claim 3
Dependent Claim
23 words
The process of claim 1 further including step (e) of repeating said steps (a)-(d) so as to write a next word of data.
Claim 4
Dependent Claim
61 words
The process of claim 1 further including the steps of: e) applying said first voltage potential to the Nth bit-line; f) applying said second voltage potential to the N-1 bit line; g) applying said first voltage potential to the Nth bit-line; h) thereafter decrementing N by unity; and i) repeating steps (e)-(h) until all bit-lines are at said first voltage potential.
Claim 5
Dependent Claim
85 words
A process for reading a cell of an array having N-bit lines and M-word lines comprising the steps of: a) accessing a word line; b) selecting a cell to be read associated with said accessed word line; c) precharging a bit line associated with said selected cell to a first voltage potential; d) applying a second voltage potential to a bit line immediately preceding said precharged bit line; and (e) applying a first voltage potential to a bit line immediately succeeding said precharged bit line.
Claim 6
Dependent Claim
85 words
A process for reading a cell of an array having N-bit lines and M-word lines comprising the steps of: a) accessing a word line; b) selecting a cell to be read associated with said accessed word line; c) precharging a bit line associated with said selected cell to a first voltage potential; d) applying a second voltage potential to a bit line immediately preceding said precharged bit line; and (e) applying a first voltage potential to a bit line immediately succeeding said precharged bit line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |