Non-volatile memory

Claim 2

A non-volatile memory comprising: (A) a cell array, said cell array comprising: (a) a plurality of memory cells arranged in a form of a matrix, each of said memory cells having first and second transistors which commonly have a floating gate and storing data therein in accordance with a quantity of electric charge accumulated in said floating gate; (b) a plurality of first gate lines associated with each of rows of said plurality of memory cells, each of said plurality of first gate lines being in electrical connection with gates of said first transistors of said memory cells disposed in an associated row; (c) a plurality of first drain lines associated with each of columns of said plurality of memory cells, each of said plurality of first drain lines being in electrical connection with drains of said first transistors of said memory cells disposed in an associated column; (d) a plurality of second gate lines associated with each of columns of said plurality of memory cells, each of said plurality of second gate lines being in electrical connection with gates of said second transistors of said memory cells disposed in an associated column; (e) a plurality of second drain lines associated with each of rows of said plurality of memory cells, each of said plurality of second drain lines being in electrical connection with drains of said second transistors of said memory cells disposed in an associated row; and (f) a plurality of source lines, each being in electrical connection with sources of said first and second transistors of each of said memory cells; (B) a first voltage applying circuit for applying one of a selection voltage and a non-selection voltage to each of said first gate lines in accordance with a first gate receiving signal; (C) a first current detecting circuit for detecting a current running through said plurality of first drain lines and correspondingly transmitting a first drain current signal; (D) a second voltage applying circuit for applying one of a selection voltage and a non-selection voltage to each of said second gate lines in accordance with a second gate receiving signal; and (E) a second current detecting circuit for detecting a current running through said plurality of second drain lines and correspondingly transmitting a second drain current signal.

Claim 3

The non-volatile memory as recited in claim 1 further comprising a source voltage switching circuit for applying a voltage for erasion to said source lines on an erasing operation and applying a ground voltage to said source lines on operations other than an erasing operation, and an eraser for applying a ground voltage to said first and second gate lines on an erasing operation.

Claim 4

The non-volatile memory as recited in claim 2, wherein said eraser is disposed in said first and second voltage applying circuits.

Claim 5

The non-volatile memory as recited in claim 1 further comprising a writer for applying a selection voltage for writing to one of said first and second gate lines, and further applying one of a selection voltage and a non-selection voltage for writing to one of said first and second drain lines on a writing operation.

Claim 6

A non-volatile memory comprising: (A) a cell array, said cell array comprising: (a) a plurality of memory cells arranged in a form of a matrix, each of said memory cells having first and second transistors which commonly have a floating gate and storing data therein in accordance with a quantity of electric charge accumulated in said floating gate; (b) a plurality of first gate lines associated with each of rows of said plurality of memory cells, each of said plurality of first gate lines being in electrical connection with gates of said first transistors of said memory cells disposed in an associated row; (c)a plurality of first drain lines associated with each of columns of said plurality of memory cells, each of said plurality of first drain lines being in electrical connection with drains of said first transistors of said memory cells disposed in an associated column; (d) a plurality of second gate lines associated with each of columns of said plurality of memory cells, each of said plurality of second gate lines being in electrical connection with gates of said second transistors of said memory cells disposed in an associated column; (e) a plurality of second drain lines associated with each of rows of said plurality of memory cells, each of said plurality of second drain lines being in electrical connection with drains of said second transistors of said memory cells disposed in an associated row; and (f) a plurality of source lines, each being in electrical connection with sources of said first and second transistors of each of said memory cells; (B) a first voltage applying circuit for applying a selection voltage to one of said plurality of first gate lines in accordance with a row address signal contained in a first gate receiving signal on a row reading operation; (C) a row reading circuit for detecting a current running through said plurality of first drain lines on a row reading operation; (D) a second voltage applying circuit for applying a selection voltage to one of said plurality of second gate lines in accordance with a column address signal contained in a second gate receiving signal on a column reading operation; and (E) a column reading circuit for detecting a current running through said plurality of second drain lines on a column reading operation.

Claim 7

A non-volatile memory comprising: (A) a cell array, said cell array comprising: (a) a plurality of memory cells arranged in a form of a matrix, each of said memory cells having first and second transistors which commonly have a floating gate and storing data therein in accordance with a quantity of electric charge accumulated in said floating gate; (b) a plurality of first gate lines associated with each of rows of said plurality of memory cells, each of said plurality of first gate lines being in electrical connection with gates of said first transistors of said memory cells disposed in an associated row; (c)a plurality of first drain lines associated with each of columns of said plurality of memory cells, each of said plurality of first drain lines being in electrical connection with drains of said first transistors of said memory cells disposed in an associated column; (d) a plurality of second gate lines associated with each of columns of said plurality of memory cells, each of said plurality of second gate lines being in electrical connection with gates of said second transistors of said memory cells disposed in an associated column; (e) a plurality of second drain lines associated with each of rows of said plurality of memory cells, each of said plurality of second drain lines being in electrical connection with drains of said second transistors of said memory cells disposed in an associated row; and (f) a plurality of source lines, each being in electrical connection with sources of said first and second transistors of each of said memory cells; (B) a first voltage applying circuit for applying a selection voltage to one of said plurality of first gate lines in accordance with a row address signal contained in a first gate receiving signal on a row reading operation; (C) a row reading circuit for detecting a current running through said plurality of first drain lines on a row reading operation; (D) a second voltage applying circuit for applying a selection voltage to one of said plurality of second gate lines in accordance with a column address signal contained in a second gate receiving signal on a column reading operation; and (E) a column reading circuit for detecting a current running through said plurality of second drain lines on a column reading operation.

Claim 8

A non-volatile memory comprising: (A) a cell array, said cell array comprising: (a) a plurality of memory cells arranged in a form of a matrix, each of said memory cells having first and second transistors which commonly have a floating gate and storing data therein in accordance with a quantity of electric charge accumulated in said floating gate; (b) a plurality of first gate lines associated with each of rows of said plurality of memory cells, each of said plurality of first gate lines being in electrical connection with gates of said first transistors of said memory cells disposed in an associated row; (c) a plurality of first drain lines associated with each of columns of said plurality of memory cells, each of said plurality of first drain lines being in electrical connection with drains of said first transistors of said memory cells disposed in an associated column; (d) a plurality of second gate lines associated with each of columns of said plurality of memory cells, each of said plurality of second gate lines being in electrical connection with gates of said second transistors of said memory cells disposed in an associated column; (e) a plurality of second drain lines associated with each of rows of said plurality of memory cells, each of said plurality of second drain lines being in electrical connection with drains of said second transistors of said memory cells disposed in an associated row; and (f) a plurality of source lines, each being in electrical connection with sources of said first and second transistors of each of said memory cells; (B) a voltage applying circuit for applying a selection voltage to one of said plurality of first gate lines in accordance with a row address signal contained in a first gate receiving signal on a row reading operation; (C) a row reading circuit for detecting a current running through said plurality of first drain lines on a row reading operation; (D) a retrieval data setting circuit for applying one of a selection voltage and a non-selection voltage to each of said plurality of second gate lines in accordance with retrieval data contained in a second gate receiving signal on a retrieving operation; and (E) a coincidence determining circuit for detecting a current running through said plurality of second drain lines on a retrieving operation.

Claim 9

A non-volatile memory comprising: (A) a cell array, said cell array comprising: (a) a plurality of memory cells arranged in a form of a matrix, each of said memory cells having first and second transistors which commonly have a floating gate and storing data therein in accordance with a quantity of electric charge accumulated in said floating gate; (b) a plurality of first gate lines associated with each of rows of said plurality of memory cells, each of said plurality of first gate lines being in electrical connection with gates of said first transistors of said memory cells disposed in an associated row; (c) a plurality of first drain lines associated with each of columns of said plurality of memory cells, each of said plurality of first drain lines being in electrical connection with drains of said first transistors of said memory cells disposed in an associated column; (d) a plurality of second gate lines associated with each of columns of said plurality of memory cells, each of said plurality of second gate lines being in electrical connection with gates of said second transistors of said memory cells disposed in an associated column; (e) a plurality of second drain lines associated with each of rows of said plurality of memory cells, each of said plurality of second drain lines being in electrical connection with drains of said second transistors of said memory cells disposed in an associated row; and (f) a plurality of source lines, each being in electrical connection with sources of said first and second transistors of each of said memory cells; (B) a voltage applying circuit for applying a selection voltage to one of said plurality of first gate lines in accordance with a row address signal contained in a first gate receiving signal on a row reading operation; (C) a row reading circuit for detecting a current running through said plurality of first drain lines on a row reading operation; (D) a retrieval data setting circuit for applying one of a selection voltage and a non-selection voltage to each of said plurality of second gate lines in accordance with retrieval data contained in a second gate receiving signal on a retrieving operation; and (E) a coincidence determining circuit for detecting a current running through said plurality of second drain lines on a retrieving operation.

Claim 10

The non-volatile memory as recited in claim 6 further comprising a source voltage switching circuit for applying a voltage for erasion to said source lines on an erasing operation and applying a ground voltage to said source lines on operations other than an erasing operation, and an eraser for applying a ground voltage to said first and second gate lines on an erasing operation.

Claim 11

The non-volatile memory as recited in claim 7, wherein said eraser is disposed in said first and second voltage applying circuits.

Claim 12

The non-volatile memory as recited in claim 6 further comprising a writer for applying a selection voltage for writing to one of said first gate lines, and further applying one of a selection voltage and a non-selection voltage for writing to one of said first drain lines on a writing operation.

Claim 13

A non-volatile memory comprising: (A) a cell array, said cell array comprising: (a) a plurality of memory means, arranged to form rows and columns, for storing data therein, each having first and second transistors which commonly have a floating gate; (b) a plurality of first gate lines, each being in electrical connection with gates of said first transistors of said memory means disposed in each of said rows; (c) a plurality of first drain lines, each being in electrical connection with drains of said first transistors of said memory means disposed in each of said columns; (d) a plurality of second gate lines, each being in electrical connection with gates of said second transistors of said memory means disposed in each of columns; (e) a plurality of second drain lines, each being in electrical connection with drains of said second transistors of said memory means disposed in each of rows; and (f) a plurality of source lines, each being in electrical connection with sources of said first and second transistors of each of said memory means; (B) means for applying one of first and second voltages to each of said first gate lines in accordance with a first input signal; (C) means for detecting a current running through said plurality of first drain lines and further transmitting a first output signal; (D) means for applying one of first and second voltages to each of said second gate lines in accordance with a second input signal; and (E) means for detecting a current running through said plurality of second drain lines and further transmitting a second output signal.

Claim 14

A non-volatile memory comprising: (A) a cell array, said cell array comprising: (a) a plurality of memory means, arranged to form rows and columns, for storing data therein, each having first and second transistors which commonly have a floating gate; (b) a plurality of first gate lines, each being in electrical connection with gates of said first transistors of said memory means disposed in each of said rows; (c) a plurality of first drain lines, each being in electrical connection with drains of said first transistors of said memory means disposed in each of said columns; (d) a plurality of second gate lines, each being in electrical connection with gates of said second transistors of said memory means disposed in each of columns; (e) a plurality of second drain lines, each being in electrical connection with drains of said second transistors of said memory means disposed in each of rows; and (f) a plurality of source lines, each being in electrical connection with sources of said first and second transistors of each of said memory means; (B) means for applying one of first and second voltages to each of said first gate lines in accordance with a first input signal; (C) means for detecting a current running through said plurality of first drain lines and further transmitting a first output signal; (D) means for applying one of first and second voltages to each of said second gate lines in accordance with a second input signal; and (E) means for detecting a current running through said plurality of second drain lines and further transmitting a second output signal.

Claim 15

The non-volatile memory as recited in claim 10 further comprising: (F) means for applying a certain voltage to said source lines on an erasing operation and applying a ground voltage to said source lines on operations other than an erasing operation; and (G) means for applying a ground voltage to said first and second gate lines on an erasing operation.

Claim 16

The non-volatile memory as recited in claim 10 further comprising means for applying a first voltage to one of said first and second gate lines, and further applying one of first and second voltages to one of said first and second drain lines on a writing operation.

Claim 17

The non-volatile memory as recited in claim 10, wherein said plurality of first gate lines and second drain lines of each row of said memory cells are replaced with a single row line.

Claim 18

The non-volatile memory as recited in claim 10, wherein said plurality of first drain lines and second gate lines of each column of said memory cells are replaced with a single column line.