Patent US5651110A successfully refreshed from Google Patents.
US5651110A
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Apparatus and method for controlling data flow between a computer and memory devices
Assignee: MICRO TECHNOLOGY CORP
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Filing: 1995-04-12
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Granted: 1997-07-22
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Expires: 2015-04-12
Abstract
Abstract A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.
Inventors
- 👤 David T. Powers
- 👤 David H. Jaffe
- 👤 Larry P. Henson
- 👤 Hoke S. Johnson, III
- 👤 Joseph S. Glider
- 👤 Thomas E. Idleman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:24
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2053; G06F11/2089; G06F11/2092; G06F11/08; G06F11/10; G06F11/1076; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/202; G06F11/2023; G06F11/2033
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
105 words
In a data storage subsystem for controlling data flow between a computer and a plurality of memory devices including a plurality of level-one controllers, independent of and coupled to said computer and a plurality of level-two controllers coupled between said level-one controllers and said memory devices, a method comprising the steps of: determining, within one of said level-one or level-two controllers that the first level-two controller has stopped functioning properly; and switching from a first level-one controller-level-two controller (LOC-LTC) path between a first level-one controller and the first level-two controller to a second LOC-LTC path between the first level-one controller and the second level-two controller.
Claim 2
Dependent Claim
105 words
In a data storage subsystem for controlling data flow between a computer and a plurality of memory devices including a plurality of level-one controllers, independent of and coupled to said computer and a plurality of level-two controllers coupled between said level-one controllers and said memory devices, a method comprising the steps of: determining, within one of said level-one or level-two controllers that the first level-two controller has stopped functioning properly; and switching from a first level-one controller-level-two controller (LOC-LTC) path between a first level-one controller and the first level-two controller to a second LOC-LTC path between the first level-one controller and the second level-two controller.
Claim 3
Dependent Claim
41 words
The method of claim 1 further comprising the step of switching from a third LOC-LTC path between a second level-one controller and the first level-two controller to a fourth LOC-LTC path between the second level-one controller and the second level-two controller.
Claim 4
Dependent Claim
29 words
The method of claim 2 further comprising the step of switching a connection to a plurality of memory devices from the first level-two controller to said second level-two controller.
Claim 5
Dependent Claim
150 words
A data storage subsystem for linking a computer to a plurality of memory devices comprising: a plurality of first-level controllers, independent of said computer and coupled to said computer, configured to handle input/output storage communications with the computer; a communication bus coupled to said first-level controllers; and first and second second-level controllers, each connected to said communication bus, said first second-level controller being connected to a first group of said memory devices, for routing data from at least one of said first-level controllers to said first group of memory devices, said second second-level controller being coupled to a second group of memory devices and said first group of memory devices, and including means, independent of said computer, for detecting a failure of said first second-level controller and re-routing data from at least one of said first-level controllers to said first group of memory devices coupled to said first second-level controller.
Claim 6
Dependent Claim
150 words
A data storage subsystem for linking a computer to a plurality of memory devices comprising: a plurality of first-level controllers, independent of said computer and coupled to said computer, configured to handle input/output storage communications with the computer; a communication bus coupled to said first-level controllers; and first and second second-level controllers, each connected to said communication bus, said first second-level controller being connected to a first group of said memory devices, for routing data from at least one of said first-level controllers to said first group of memory devices, said second second-level controller being coupled to a second group of memory devices and said first group of memory devices, and including means, independent of said computer, for detecting a failure of said first second-level controller and re-routing data from at least one of said first-level controllers to said first group of memory devices coupled to said first second-level controller.
Claim 7
Dependent Claim
45 words
The data storage subsystem of claim 4 further comprising first communication lines connected between each of said plurality of second-level controllers, and means, in each of said second-level controllers coupled to said first communication lines, for informing another second-level controller that a failure has occurred.
Claim 8
Dependent Claim
45 words
The data storage subsystem of claim 4 further comprising switching means, connected between said plurality of second-level controllers and said groups of memory devices, for reconnecting one of said groups of memory devices from a first second-level controller upon failure to a different second-level controller.
Claim 9
Dependent Claim
44 words
The data storage subsystem of claim 4 further comprising, in each said second-level controllers, means for detecting a complete failure of another one of said second-level controllers, said complete failure being indicated by the inability of said another second-level controller to communicate its failure.
Claim 10
Dependent Claim
48 words
The data storage subsystem of claim 4 further comprising means, in each of said second-level controllers, for communicating a controlled failure of said second-level controller to others of said second-level controller, said controlled failure being indicated by said second-level controller being able to communicate that it is failing.
Claim 11
Dependent Claim
86 words
The data storage subsystem of claim 4 wherein each of said second-level controllers includes a controller recovery state machine for responding to the failure of one of said second-level controllers, said state machine including the following states: a primary state wherein said second-level controller is connected to a group of said memory devices; a none state wherein said second-level controller is not connected to any of said memory devices; and a both state wherein said second-level controller is connected to two groups of said memory devices.
Claim 12
Dependent Claim
73 words
The data storage subsystem of claim 9 further comprising: a run-down state between said primary and said none states for performing transition functions between said primary and none states; said primary state being responsive to a diagnostic testing signal provided to said second-level controller from an external source to transition to said run-down state; and means, responsive to said run-down state, for transmitting a controlled failure signal to another of said second-level controllers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-21 | 2001-01-20 | 2001-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-21 | 2005-01-20 | 2005-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-21 | 2009-01-20 | 2009-07-22 | $7700.00 | Window Closed / Lapsed |