Flash EEPROM system cell array with more than two storage states per memory cell

Claim 1

For an array of electrically alterable memory cells divided into blocks of cells and having means for addressing individual cells within said blocks to read and alter their states, said memory cells individually including a field effect transistor with a floating gate and having a threshold voltage level that is a given level in the absence of net charge on said floating gate but which is variable in accordance with an amount of net charge carried by said floating gate, a method of operating the array, comprising: establishing a plurality of effective threshold voltage levels in excess of two that correspond to a plurality of detectable programmed states of the individual cells in excess of two, setting the effective threshold voltage level of at least one addressed cell within one of said blocks from a starting level to one of the plurality of threshold voltage levels by altering the amount of charge on the floating gate of said addressed cell until the effective threshold voltage of said addressed cell is substantially equal to one of said plurality of effective threshold voltage levels, whereby the state of said addressed cell is set to one of said plurality of programmed states, setting the effective threshold voltage level including the steps of: applying a given voltage to said addressed cell for a predetermined time sufficient to move the effective threshold voltage level of the addressed cell from the starting level toward said one of the plurality of threshold voltage levels, thereafter reading an electrical parameter of the addressed cell to determine whether the effective threshold voltage of the addressed cell has reached said one of the plurality of threshold voltage levels, and repeating the voltage applying and reading steps until it is detected by the reading step that the effective threshold voltage of the addressed cell has been set to said one of the plurality of threshold voltage levels.

Claim 9

The method of any one of claims 1-7 wherein at least two of said plurality of effective threshold levels result from a net positive charge on the floating gate of the individual cells.

Claim 10

The method of any one of claims 1-7 wherein the given threshold level of the individual cells is established to be at least three volts.

Claim 11

The method of any one of claims 1-7 wherein the repeating of the voltage applying and reading steps during setting the effective threshold voltage level of said at least one addressed cell is terminated after a preset maximum number of repeats of the voltage applying and reading steps have occurred during setting without setting the effective threshold voltage levels of the addressed cell to said one of the plurality of threshold voltage levels.

Claim 12

The method of any one of claims 1-7 wherein the repeating of the voltage applying and reading steps during resetting the effective threshold voltage levels of cells within said at least one block is terminated after a preset maximum number of repeats of the voltage applying and reading steps have occurred during resetting without resetting the effective threshold voltage level of a certain number of the individual cells within said at least one block to said preset level.

Claim 13

The method of any one of claims 1-7 which additionally comprises, in response to said at least one addressed cell becoming defective, of substituting therefore a redundant good cell within the array.

Claim 14

The method of any one of claims 1-7 which additionally comprises, in response to said at least one block of cells becoming defective, of substituting therefore at least one redundant block of cells within the array.

Claim 15

The method of any one of claims 1-7 which additionally comprises accumulating a count of a total number of times that at least one block of cells has been reset.