US5642307A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Die identifier and die indentification method
Assignee: GlobalFoundries Inc
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Filing: 1994-06-30
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Granted: 1997-06-24
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Expires: 2014-06-30
Abstract
Abstract An identification section fabricated onto a semiconductor integrated circuit includes structure for storing die-specific information that characterizes that particular integrated circuit. The identification section may also include structure for reading the die-specific information from the structure for storing. In addition or otherwise, the identification section may also include structure for programming the die-specific information into the structure for storing.
Inventors
- 👤 Clark W. Jernigan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:04
CPC Classifications
H; H10; H10W; H10W46/00; G; G06; G06F; G06F11/00; G06F11/006; H10D; H10D89/00; H10W46/401; H10W46/601
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
81 words
A die comprising: a first integrated circuit portion; and a second integrated circuit portion, said first and said second integrated circuit portions being adjacent each other on said die, said second integrated circuit portion comprising: at least one bidirectional die pad; programming circuitry connected to said at least one bidirectional die pad; a memory section connected to said programming circuitry for storing a die specific information; output circuitry connected to said memory section and said at least one bidirectional die pad.
Claim 2
Dependent Claim
81 words
A die comprising: a first integrated circuit portion; and a second integrated circuit portion, said first and said second integrated circuit portions being adjacent each other on said die, said second integrated circuit portion comprising: at least one bidirectional die pad; programming circuitry connected to said at least one bidirectional die pad; a memory section connected to said programming circuitry for storing a die specific information; output circuitry connected to said memory section and said at least one bidirectional die pad.
Claim 3
Dependent Claim
37 words
The die as set forth in claim 1, further comprising: a unidirectional die pad, said unidirectional die pad being electrically connectable to at least one of said first integrated circuit portion and said second integrated circuit portion.
Claim 4
Dependent Claim
19 words
The die as set forth in claim 1, wherein said memory section comprises a plurality of non-volatile memory cells.
Claim 5
Dependent Claim
18 words
The die as set forth in claim 1, wherein said memory section comprises a plurality of fusible links.
Claim 6
Dependent Claim
18 words
The die as set forth in claim 1, wherein said memory section comprises a plurality of laser-blown fuses.
Claim 7
Dependent Claim
31 words
The die as set forth in claim 1, wherein said die specific information includes a fabrication lot number, said fabrication lot number identifying a fabrication lot from which the die originated.
Claim 8
Dependent Claim
28 words
The die as set forth in claim 1, wherein said die specific information includes a wafer number, said wafer number identifying a wafer from which the die originated.
Claim 9
Dependent Claim
37 words
The die as set forth in claim 1, wherein said die specific information includes a die position information, said die position information relating to the position of the die on a wafer from which the die originated.
Claim 10
Dependent Claim
27 words
The die as set forth in claim 1, wherein said die specific information includes at least one of a design rule information and a process history information.
Claim 11
Independent Claim
77 words
An apparatus for providing a user with semiconductor processing and test information relating to a first circuit disposed on a semiconductor die, the apparatus comprising: a storage structure having a plurality of storage locations disposed on said semiconductor die adjacent said first circuit; means for storing said semiconductor processing and test information into at least a subset of said plurality of storage locations; and bidirectional access means for accessing said subset of said plurality of storage locations.
Claim 12
Independent Claim
77 words
An apparatus for providing a user with semiconductor processing and test information relating to a first circuit disposed on a semiconductor die, the apparatus comprising: a storage structure having a plurality of storage locations disposed on said semiconductor die adjacent said first circuit; means for storing said semiconductor processing and test information into at least a subset of said plurality of storage locations; and bidirectional access means for accessing said subset of said plurality of storage locations.
Claim 13
Dependent Claim
21 words
The apparatus as set forth in claim 10, wherein said plurality of storage locations comprises a plurality of non-volatile memory cells.
Claim 14
Dependent Claim
20 words
The apparatus as set forth in claim 10, wherein said plurality of storage locations comprises a plurality of fusible links.
Claim 15
Dependent Claim
20 words
The apparatus as set forth in claim 10, wherein said plurality of storage locations comprises a plurality of laser-blown fuses.
Claim 16
Independent Claim
102 words
A device for providing users with semiconductor processing and test information relating to a primary circuit disposed on a semiconductor chip, said device comprising: storage means disposed on said semiconductor chip for storing said semiconductor processing and test information, said storage means being electrically isolated from said primary circuit; input means for accessing at least a portion of said storage means; programming means for programming said semiconductor processing and test information into said portion of said storage means; and output means for providing output signals representative of said semiconductor processing and test information when said portion of said storage means is accessed.
Claim 17
Independent Claim
102 words
A device for providing users with semiconductor processing and test information relating to a primary circuit disposed on a semiconductor chip, said device comprising: storage means disposed on said semiconductor chip for storing said semiconductor processing and test information, said storage means being electrically isolated from said primary circuit; input means for accessing at least a portion of said storage means; programming means for programming said semiconductor processing and test information into said portion of said storage means; and output means for providing output signals representative of said semiconductor processing and test information when said portion of said storage means is accessed.
Claim 18
Dependent Claim
19 words
The device as set forth in claim 14, wherein said storage means comprises a plurality of non-volatile memory cells.
Claim 19
Dependent Claim
18 words
The device as set forth in claim 14, wherein said storage means comprises a plurality of fusible links.
Claim 20
Dependent Claim
18 words
The device as set forth in claim 14, wherein said storage means comprises a plurality of laser-blown fuses.
Claim 21
Dependent Claim
18 words
The device as set forth in claim 14, wherein said storage means comprises a plurality of read-only-memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-23 | 2000-12-23 | 2001-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-23 | 2004-12-23 | 2005-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-23 | 2008-12-23 | 2009-06-24 | $7700.00 | Window Closed / Lapsed |