US4419747A
Expired / Lapsed
US
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Method and device for providing process and test information in semiconductors
Assignee: SEEZ TECHNOLOGY Inc
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Filing: 1982-02-05
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Granted: 1983-12-06
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Expires: 2002-02-05
Abstract
Abstract A method and system for encoding key process and test information in semiconductors is disclosed. The invention is particularly useful in connection with byte-wide memories, but also finds application in a wide range of semiconductor devices. A plurality of programmable memory cells are juxtaposed on a semiconductor die with the circuitry which performs the primary function of the chip. The programmable memory cells are interconnected with the primary circuit in such a manner that the information programmed and stored therein can be accessed only when such access does not interfere with the operation of the primary circuit. Important product processing and test information is stored in the programmable cells such as wafer number, lot number, processing parameters, special visual and test results and manufacturing rework data.
Inventors
- 👤 Larry T. Jordan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:53
CPC Classifications
G; G11; G11C; G11C5/00; G11C17/00; G11C17/08; G11C8/00
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
104 words
A device for providing a user with semiconductor processing and test information relating to a primary circuit disposed upon a semiconductor chip, said device comprising: a programmable memory array having a plurality of storage locations disposed on the semiconductor chip adjacent the primary circuit; addressing means for accessing selected individual storage locations in said plurality of storage locations; programming means for programming semiconductor processing and test information into said selected storage locations accessed by said addressing means; and output means for providing output signals representative of the semiconductor processing and test information programmed into said selected individual storage locations accessed by said addressing means.
Claim 2
Independent Claim
104 words
A device for providing a user with semiconductor processing and test information relating to a primary circuit disposed upon a semiconductor chip, said device comprising: a programmable memory array having a plurality of storage locations disposed on the semiconductor chip adjacent the primary circuit; addressing means for accessing selected individual storage locations in said plurality of storage locations; programming means for programming semiconductor processing and test information into said selected storage locations accessed by said addressing means; and output means for providing output signals representative of the semiconductor processing and test information programmed into said selected individual storage locations accessed by said addressing means.
Claim 3
Dependent Claim
13 words
The device of claim 1 wherein said programmable memory array comprises fusible links.
Claim 4
Dependent Claim
14 words
The device of claim 1 wherein said programmable memory array comprises laser blown fuses.
Claim 5
Dependent Claim
14 words
The device of claim 1 wherein said programmable memory array comprises non-volatile memory cells.
Claim 6
Dependent Claim
23 words
The device of claim 1 wherein said addressing means includes logic means for alternately accessing the primary circuit and said programmable memory array.
Claim 7
Dependent Claim
47 words
The device of claim 5 wherein the primary circuit is a semiconductor memory having a plurality of storage locations arranged to form a primary memory array and said addressing means is common to said programmable memory array and at least a portion of the primary memory array.
Claim 8
Dependent Claim
76 words
The device of claim 6 wherein said addressing means further includes an address pin with a decoder means connected thereto for addressing a predetermined storage location in the primary memory array when a first signal is applied to said address pin and said logic means includes a detection means connected to said address pin for accessing said programmable memory array while simultaneously disabling said decoder means when a second signal is applied to said address pin.
Claim 9
Dependent Claim
30 words
The device of claim 6 wherein the primary memory array comprises rows and columns of memory cells and said programmable memory array comprises one of said columns of memory cells.
Claim 10
Dependent Claim
12 words
The device of claim 8 wherein said memory cells comprise fusible links.
Claim 11
Dependent Claim
13 words
The device of claim 8 wherein said memory cells comprise laser blown fuses.
Claim 12
Dependent Claim
13 words
The device of claim 8 wherein said memory cells comprise non-volatile memory cells.
Claim 13
Dependent Claim
30 words
The device of claim 6 wherein the primary memory array comprises rows and columns of memory cells and said programmable memory array comprises one of said rows of memory cells.
Claim 14
Dependent Claim
12 words
The device of claim 12 wherein said memory cells comprise fusible links.
Claim 15
Dependent Claim
13 words
The device of claim 12 wherein said memory cells comprise laser blown fuses.
Claim 16
Dependent Claim
13 words
The device of claim 12 wherein said memory cells comprise non-volatile memory cells.
Claim 17
Independent Claim
140 words
A device for providing a user with semiconductor processing and test information relating to a primary memory array having storage locations disposed upon a semiconductor chip, said device comprising: a secondary programmable memory array having a plurality of storage locations disposed on the semiconductor chip adjacent the primary memory array; addressing means for accessing the storage locations in the primary memory array and for the alternately accessing said plurality of storage locations in said secondary programmable memory array; programmable means for selectively programming said semiconductor processing and test information into said plurality of storage locations in said secondary programmable memory array when said addressing means accesses said plurality of storage locations in said secondary programmable memory array; and output means for providing output signals representative of said information programmed into said plurality of storage locations in said secondary memory array.
Claim 18
Independent Claim
140 words
A device for providing a user with semiconductor processing and test information relating to a primary memory array having storage locations disposed upon a semiconductor chip, said device comprising: a secondary programmable memory array having a plurality of storage locations disposed on the semiconductor chip adjacent the primary memory array; addressing means for accessing the storage locations in the primary memory array and for the alternately accessing said plurality of storage locations in said secondary programmable memory array; programmable means for selectively programming said semiconductor processing and test information into said plurality of storage locations in said secondary programmable memory array when said addressing means accesses said plurality of storage locations in said secondary programmable memory array; and output means for providing output signals representative of said information programmed into said plurality of storage locations in said secondary memory array.
Claim 19
Independent Claim
167 words
A device for providing a user with semiconductor processing and test information relating to a primary memory array having storage locations disposed upon a semiconductor chip, said device comprising; a secondary programmable memory array having a plurality of storage locations disposed on the semiconductor chip adjacent the primary memory array; addressing means for accessing the storage locations in the primary memory array and for alternately accessing said plurality of storage locations in said secondary programmable memory array; programming means for selectively programming said semiconductor processing and test information into said plurality of storage locations in said secondary programmable memory array when said addressing means accesses said plurality of storage locations in said secondary programmable memory array; and output means for providing a first set of output signals representative of the information programmed into the storage locations in the primary memory array and for alternately providing a second set of output signals representative of said information programmed into said plurality of storage locations in said secondary memory array.
Claim 20
Independent Claim
167 words
A device for providing a user with semiconductor processing and test information relating to a primary memory array having storage locations disposed upon a semiconductor chip, said device comprising; a secondary programmable memory array having a plurality of storage locations disposed on the semiconductor chip adjacent the primary memory array; addressing means for accessing the storage locations in the primary memory array and for alternately accessing said plurality of storage locations in said secondary programmable memory array; programming means for selectively programming said semiconductor processing and test information into said plurality of storage locations in said secondary programmable memory array when said addressing means accesses said plurality of storage locations in said secondary programmable memory array; and output means for providing a first set of output signals representative of the information programmed into the storage locations in the primary memory array and for alternately providing a second set of output signals representative of said information programmed into said plurality of storage locations in said secondary memory array.
Claim 21
Dependent Claim
46 words
A device as set forth in claim 17 wherein said addressing means includes a logic means for generating a signal which accesses said secondary programmable memory array while disabling the primary memory array and which simultaneously connects said output means to said secondary programmable memory array.
Claim 22
Independent Claim
93 words
A method for providing semiconductor processing and test information relating to a primary memory array in a semiconductor device having a programmable non-volatile storage means formed thereon adjacent to said primary array and also having an addressing means formed thereon for alternately accessing said primary memory array and said programmable non-volatile storage means, said method comprising the steps of: accessing said programmable non-volatile storage means; programming into said non-volatile storage means selected semiconductor processing and test information relating to said primary circuit; and retrieving said selected information from said storage means on demand.
Claim 23
Independent Claim
93 words
A method for providing semiconductor processing and test information relating to a primary memory array in a semiconductor device having a programmable non-volatile storage means formed thereon adjacent to said primary array and also having an addressing means formed thereon for alternately accessing said primary memory array and said programmable non-volatile storage means, said method comprising the steps of: accessing said programmable non-volatile storage means; programming into said non-volatile storage means selected semiconductor processing and test information relating to said primary circuit; and retrieving said selected information from said storage means on demand.
Claim 24
Dependent Claim
26 words
A method as set forth in claim 19, further including the step of disabling said primary memory array when said programmable non-volatile storage means is accessed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-05 | 1987-06-06 | 1987-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-05 | 1991-06-06 | 1991-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-05 | 1995-06-06 | 1995-12-06 | $7700.00 | Window Closed / Lapsed |