EP0420388A2
Expired / Lapsed
EP
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Test latch circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1990-06-29
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Granted: —
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Expires: 2010-06-29
Abstract
Abstract A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile memory elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.
Inventors
- 👤 Bruce Andrew Doyle
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 15:24
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G11C29/52
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
76 words
A test circuit for use in an integrated circuit device, comprising: an output signal line coupled to said non-volatile memory element; a latch coupled to said output signal line; and means for setting a value for said latch during testing, wherein a value of said outut signal line is determined by the latch value during testing, and wherein the output signal line value is determined by a value of said non-volatile memory element except during testing.
Claim 2
Dependent Claim
76 words
A test circuit for use in an integrated circuit device, comprising: an output signal line coupled to said non-volatile memory element; a latch coupled to said output signal line; and means for setting a value for said latch during testing, wherein a value of said outut signal line is determined by the latch value during testing, and wherein the output signal line value is determined by a value of said non-volatile memory element except during testing.
Claim 3
Dependent Claim
34 words
The device of Claim 1, wherein said latch value setting means comprises a transistor switch connected to said latch and to a programmed bit value, said switch being controlled by a test programming signal.
Claim 4
Dependent Claim
33 words
The device of Claim 2, wherein the programmed bit value is also coupled to said non-volatile memory element, wherein said non-volatile device is programmed during a normal programming by the programmed bit value.
Claim 5
Dependent Claim
32 words
The device of Claim 3, wherein the programmed bit value is coupled to said non-volatile memory element through a second transistor switch, said second switch being controlled by a normal programming signal.
Claim 6
Dependent Claim
46 words
The device of Claim 1, wherein said non-volatile memory element comprises: a memory storage cell; and an output stage having an inverter and a pullup load element at an input to the inverter, wherein an output of the inverter is connected to the output signal line.
Claim 7
Dependent Claim
29 words
The device of Claim 5, wherein said latch comprises: a transistor switch connected between the inverter input and ground, and having a control input connected to the inverter output.
Claim 8
Independent Claim
70 words
A method for programming a configuration bit during testing of an integrated circuit, comprising the steps of: providing a non-volatile memory element and a latch connected to a configuration bit signal line; during testing, setting a value in the latch to control a value of the configuration bit signal line; and otherwise, controlling the value of the configuration bit signal line by a value stored in the non-volatile memory element.
Claim 9
Independent Claim
70 words
A method for programming a configuration bit during testing of an integrated circuit, comprising the steps of: providing a non-volatile memory element and a latch connected to a configuration bit signal line; during testing, setting a value in the latch to control a value of the configuration bit signal line; and otherwise, controlling the value of the configuration bit signal line by a value stored in the non-volatile memory element.
References Cited (Backward Citations)
No citation records indexed.
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