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US4510673A Expired / Lapsed US ⏱️ 0.0 years remaining

Laser written chip identification method

Assignee: International Business Machines Corp
•
Filing: 1983-06-23
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Granted: 1985-04-16
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Expires: 2003-06-23
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Abstract

Abstract A system of identifying each chip with identification data that is both human and machine readable. The chip identification is then used in sorting, storing, testing, assembling and failure analysis. The identification usage at these process steps eliminates chip part number mix-up and placement. It provides data used for quality control.

Inventors

  • 👤 Alan J. Shils
  • 👤 John P. Ianni, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 19:25
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/10861; B; B07; B07C; B07C5/00; B07C5/34; B07C5/3412; H; H10; H10W; H10W46/00; H10W46/601; Y; Y10; Y10S; Y10S438/00; Y10S438/94

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 128 words
A method of producing a semiconductor device comprising the steps of: providing a plurality of semiconductor chips on a wafer and testing said chips on said wafer to determine their useability; writing on each chip identification data that may be read by a human or a machine; dicing said wafer to separate said chips; selecting and placing said chips into a storage device and reading said identification data to verify the proper location and orientation of said chips in said storage device; removing said chips from said storage device and placing said chips on a substrate; reading said identification data to verify the correct location and orientation of each chip on said substrate and, if incorrect, re-locating and/or re-orienting said chip; and joining said chips to said substrate.
Claim 2
Independent Claim 128 words
A method of producing a semiconductor device comprising the steps of: providing a plurality of semiconductor chips on a wafer and testing said chips on said wafer to determine their useability; writing on each chip identification data that may be read by a human or a machine; dicing said wafer to separate said chips; selecting and placing said chips into a storage device and reading said identification data to verify the proper location and orientation of said chips in said storage device; removing said chips from said storage device and placing said chips on a substrate; reading said identification data to verify the correct location and orientation of each chip on said substrate and, if incorrect, re-locating and/or re-orienting said chip; and joining said chips to said substrate.
Claim 3
Dependent Claim 36 words
The method of claim 1 further comprising the steps of testing said module and, if unacceptable, removing a defective chip and writing on that chip further identification data indicative of the failure mode of said chip.
Claim 4
Dependent Claim 24 words
The method of claim 1 further comprising the step of performing failure analysis on semiconductor devices returned from actual use utilizing said identification data.
Claim 5
Dependent Claim 28 words
The method of claim 1, wherein the step of writing identification data comprises the step of writing indicia on the back of said chip indicative of manufacture parameters.
Claim 6
Dependent Claim 18 words
The method of claim 4, wherein said writing is a laser written character using a laser scribing tool.
Claim 7
Dependent Claim 51 words
The method of claim 1, wherein the step of selecting and placing said chips into a storage device comprises the steps of laser reading said identification data on said chips after said chips have been placed in said storage device and, resorting and/or re-orienting any chip not properly located and/or oriented.
Claim 8
Dependent Claim 14 words
The method of claim 6, wherein said storage device is a chip collection bank.
Claim 9
Dependent Claim 30 words
The method of claim 1, wherein the step of joining said chips to said substrate comprises the step of reflow soldering terminals on said chip to terminals on said substrate.
Claim 10
Dependent Claim 19 words
The method of claim 1, wherein the step of reading comprising non-electric, non-contact reading of said chip identification data.
Claim 11
Dependent Claim 16 words
The method of claim 9, wherein said non-electric, non-contact reading is optical scanning of said chip.

References Cited (Backward Citations)

US4027246A Cited
US4166574A Cited
US4150331A Cited
JPS568836A Cited
US4419747A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-04-15 1988-10-15 1989-04-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-04-15 1992-10-15 1993-04-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-04-15 1996-10-15 1997-04-16 $7700.00 Window Closed / Lapsed

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