Patent US5638542A successfully refreshed from Google Patents.
US5638542A
Expired / Lapsed
US
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Low power non-overlap two phase complementary clock unit using synchronous delay line
Assignee: Intel Corp
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Filing: 1996-05-06
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Granted: 1997-06-10
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Expires: 2016-05-06
Abstract
Abstract A clock generator which utilizes a SDL, power management circuitry, phase drivers and non-overlap logic all integrated on a single chip to output a set of non-overlapped, complementary clock phases for each processor and for on board peripherals. The present invention also has application for use with multiple discrete processors used on an application or system validation board where one or more of the processors may run at different clock speeds from the others or be stopped. The integrated non-overlap logic reduces the clock skewing among various component on the application board, thus, increasing the overall performance of the system. The present invention is specifically directed to clock generation circuitry including a circuit which receives clock phases generated by a SDL, or from a set of frequency dividers and produces non-overlapped clock phases for each on-board processor and for the on-board peripherals.
Inventors
- 👤 Bobby B. Nikjou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:24
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3287; G06F1/04; G06F1/06; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
139 words
A multiple microprocessor integrated circuit comprising: a) a clock unit including power management circuitry means for placing the integrated circuit unit into a predetermined power management mode and non-overlap clock phase logic circuitry means for generating non-overlapped clock signals; b) a general purpose microprocessor which receives first clock signals from said clock unit; c) at least one additional microprocessor, each of which receives one of a set of second clock signals from said clock unit, d) a set of peripherals which receives third clock signals from said clock unit, wherein said non-overlap clock phase logic circuitry means generates separate phase 1 clocks and phase 2 clocks for each of said first clock signals, each of said set of second clock signals and said third clock signals such that each of said phase 1 and phase 2 clocks are non-overlapped.
Claim 2
Dependent Claim
139 words
A multiple microprocessor integrated circuit comprising: a) a clock unit including power management circuitry means for placing the integrated circuit unit into a predetermined power management mode and non-overlap clock phase logic circuitry means for generating non-overlapped clock signals; b) a general purpose microprocessor which receives first clock signals from said clock unit; c) at least one additional microprocessor, each of which receives one of a set of second clock signals from said clock unit, d) a set of peripherals which receives third clock signals from said clock unit, wherein said non-overlap clock phase logic circuitry means generates separate phase 1 clocks and phase 2 clocks for each of said first clock signals, each of said set of second clock signals and said third clock signals such that each of said phase 1 and phase 2 clocks are non-overlapped.
Claim 3
Dependent Claim
145 words
A circuit including a clock generator for use with discrete microprocessors comprising: a) a clock unit including power management circuitry means for placing the integrated circuit unit into a predetermined power management mode and non-overlap clock phase logic circuitry means for generating non-overlapped clock signals; b) a general purpose microprocessor which receives first clock signals from said clock unit; c) at least one additional microprocessor, each of which receives one of a set of second clock signals from said clock unit, d) a set of peripherals which receives third clock signals from said clock unit, wherein said non-overlap clock phase logic circuitry means generates separate phase 1 clocks and phase 2 clocks for each of said first clock signals, each of said set of second clock signals and said third clock signals such that each of said phase 1 and phase 2 clocks are non-overlapped.
Claim 4
Dependent Claim
145 words
A circuit including a clock generator for use with discrete microprocessors comprising: a) a clock unit including power management circuitry means for placing the integrated circuit unit into a predetermined power management mode and non-overlap clock phase logic circuitry means for generating non-overlapped clock signals; b) a general purpose microprocessor which receives first clock signals from said clock unit; c) at least one additional microprocessor, each of which receives one of a set of second clock signals from said clock unit, d) a set of peripherals which receives third clock signals from said clock unit, wherein said non-overlap clock phase logic circuitry means generates separate phase 1 clocks and phase 2 clocks for each of said first clock signals, each of said set of second clock signals and said third clock signals such that each of said phase 1 and phase 2 clocks are non-overlapped.
Claim 5
Dependent Claim
19 words
The circuit defined by claim 1 where said predetermined power management modes are one of powerdown, idle and standby.
Claim 6
Dependent Claim
19 words
The circuit defined by claim 2 where said predetermined power management modes are one of powerdown, idle and standby.
Claim 7
Dependent Claim
55 words
The circuit defined by claim 1 wherein said power management circuitry means comprises a logic circuit which generates signals which indicate that i) the integrated circuit is in one of an idle mode, a power down mode, a stand-by mode, and ii) at least one of the at least one additional microprocessors is temporarily stopped.
Claim 8
Dependent Claim
64 words
The circuit defined by claim 1 wherein said non-overlap clock phase logic circuitry means comprises logic circuits which operate cooperatively to generate said phase 1 clocks and said phase 2 clocks for each of said first clock signals, each of said set of second clock signals, and said third clock signals, such that each of said phase 1 and phase 2 clocks are non-overlapped.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |