US4816700A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-phase non-overlapping clock generator
Assignee: Intel Corp
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Filing: 1987-12-16
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Granted: 1989-03-28
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Expires: 2007-12-16
Abstract
Abstract An external timing source (40) provides an input waveform (44, 46) of signal voltage transitions which occur at a first frequency, which is twice the frequency desired by the internal clock. A divider circuit (48) divides the input waveform (44, 46) into a pair of intermediate waveforms (60, 62). The intermediate waveforms have signal-voltage transitions of opposing polarity which occur at a second frequency that is one-half of the first frequency. The input waveforms and the intermediate waveforms are supplied to a driver circuit (64). The driver circuit utilizes the intermediate waveforms occurring at the divided-down frequency and the input waveform occurring at the system clock frequency to produce a pair of final waveforms (66, 68). The final waveforms have signal voltage transistions of opposing polarity occurring at the divided-down frequency, but triggerred by and in synchronism with the input waveform occurring at the external clock frequency.
Inventors
- 👤 Michael T. Imel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:53
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515; H03K5/15013; H03K5/1506
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
335 words
A clock signal generator comprising: a clock buffer for providing a first input waveform of first signal voltage transitions occurring at a first frequency and a second input waveform of second signal voltage transitions of polarity opposite to the polarity of said first signal voltage transitions, said second signal voltage transitions occurring at said first frequency; frequency divider means connected to said buffer; said frequency divider means including first means for dividing said first waveform into a first intermediate waveform of second signal voltage transitions occurring at a second frequency which is a fraction of said first frequency and second means for dividing said second waveform into a second intermediate waveform of second signal voltage transitions occurring at said second frequency and, driver means connected to said clock buffer and to said frequency divider means, said driver means including first circuit means and second circuit means for utilizing said first and second intermediate waveforms occurring at said second frequency and said first and second input waveforms occurring at said first frequency to produce a pair of final waveform outputs of signal voltage transitions of opposing polarity occurring at said second frequency. said first circuit means receiving as an input one of said final waveform output, said first circuit means further including means responsive to other said final waveform outputs (68) for causing said output to change to one level upon the condition that said DELIN input goes to the opposite level, said second circuit means receiving as an input other said final waveform outputs, said second circuit means further including means responsive to one of said final waveform outputs for causing said output to change to one level upon the condition that said DELIN output goes to the opposite level, thereby ensuring that said final waveforms do not overlap one another, each of said first and second circuit means further including means responsive to said input waveform for synchronizing said final waveforms with said first and second signal voltage transitions occurring at said first frequency.
Claim 2
Dependent Claim
335 words
A clock signal generator comprising: a clock buffer for providing a first input waveform of first signal voltage transitions occurring at a first frequency and a second input waveform of second signal voltage transitions of polarity opposite to the polarity of said first signal voltage transitions, said second signal voltage transitions occurring at said first frequency; frequency divider means connected to said buffer; said frequency divider means including first means for dividing said first waveform into a first intermediate waveform of second signal voltage transitions occurring at a second frequency which is a fraction of said first frequency and second means for dividing said second waveform into a second intermediate waveform of second signal voltage transitions occurring at said second frequency and, driver means connected to said clock buffer and to said frequency divider means, said driver means including first circuit means and second circuit means for utilizing said first and second intermediate waveforms occurring at said second frequency and said first and second input waveforms occurring at said first frequency to produce a pair of final waveform outputs of signal voltage transitions of opposing polarity occurring at said second frequency. said first circuit means receiving as an input one of said final waveform output, said first circuit means further including means responsive to other said final waveform outputs (68) for causing said output to change to one level upon the condition that said DELIN input goes to the opposite level, said second circuit means receiving as an input other said final waveform outputs, said second circuit means further including means responsive to one of said final waveform outputs for causing said output to change to one level upon the condition that said DELIN output goes to the opposite level, thereby ensuring that said final waveforms do not overlap one another, each of said first and second circuit means further including means responsive to said input waveform for synchronizing said final waveforms with said first and second signal voltage transitions occurring at said first frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-27 | 1992-09-26 | 1993-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-27 | 1996-09-26 | 1997-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-27 | 2000-09-26 | 2001-03-28 | $7700.00 | Window Closed / Lapsed |