CMOS D-type flip-flop circuits

Claim 1

A CMOS D-type flip-flop circuit for avoiding the possibility of feedthrough comprising: a non-overlapping clock generator section having a true clock output and a complement clock output; a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate; said first transfer gate being formed of a first N-channel MOS transistor with common electrodes and a gate electrode, and said first regenerative transistor being formed of a first P-channel MOS transistor with common electrodes and a gate electrode; said first N-channel transistor having one of its common electrodes connected to a D input terminal, its other common electrode connected to the input of said first inverter gate and its gate electrode connected to the complement clock output; said first P-channel transistor having one of its common electrodes connected to a supply potential, its other common electrode connected to the input of said first inverter gate, and its gate electrode connected to the output of said first inverter gate; said first inverter gate being formed of a P-channel MOS transistor and an N-channel MOS transistor whose gate electrodes are connected together to define the input thereof and whose drain electrodes are connected together to define the output thereof; a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate; said second transfer gate being formed of a second N-channel MOS transistor with common electrodes and a gate electrode, and said second regenerative transistor being formed of a second P-channel MOS transistor with common electrodes and a gate electrode; said second N-channel transistor having one of its common electrodes connected to the output of said first inverter gate, its other common electrode connected to the input of said second inverter gate and its gate electrode connected to the true clock output; said second P-channel transistor having one of its common electrodes connected to the supply potential, its other common electrode connected to the input of said second inverter gate and its gate electrode connected to the output of said second inverter gate and to an output terminal; said second inverter gate being formed of a P-channel MOS transistor and an N-channel MOS transistor whose gate electrodes are connected together to define the input thereof and whose drain electrodes are connected together to define the output thereof; a first regeneration circuit formed of a third inverter gate and a third N-channel MOS transistor with common electrodes and a gate electrode; said third N-channel transistor having one of its common electrodes connected to the output of said third inverter gate, its other common electrode connected to the input of said first inverter gate and its gate electrode connected to the true clock output, the input of said third inverter gate being connected to the output of said first inverter gate; a second regeneration circuit formed of a fourth inverter gate and a fourth N-channel MOS transistor with common electrodes and a gate electrode; and said fourth N-channel transistor having one of its common electrodes connected to the output of said fourth inverter gate, its other common electrode connected to the input of said second inverter gate and its gate electrode connected to the complementary clock output, the input of said fourth inverter gate being connected to the output of said second inverter gate.