Patent EP0164959A2 successfully refreshed from Google Patents.
Patent US5638320A successfully refreshed from Google Patents.
US5638320A
Expired / Lapsed
US
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High resolution analog storage EPROM and flash EPROM
Assignee: SanDisk Technologies LLC
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Filing: 1996-01-11
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Granted: 1997-06-10
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Expires: 2016-01-11
Abstract
Abstract Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read process determines a memory cell's threshold voltage by slowly ramping the control gate voltage and sensing when the cell conducts. Another read process slowly ramps the source voltage of a memory cell and determines the cell's threshold voltage from the drain voltage of the memory cell. Still another read process connects a cascoding device to a memory cell and biases the memory cell in the linear region while the threshold voltage of the memory cell is determined from a voltage across a load which carries a current that mirrors the current through the memory cell. Read processes disclosed for analog memory cells also apply to binary memory cells, multilevel digital memory cells, and other applications which require precise reading of threshold voltages.
Inventors
- 👤 Sau C. Wong
- 👤 Hock C. So
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:54
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C27/00; G11C27/005; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5621; G11C7/00; G11C7/16
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
114 words
A method for reading a threshold voltage of a memory cell, comprising: connecting the memory cell, a cascoding device, and a first transistor in series between a voltage supply and ground, wherein the first transistor has a gate coupled to its drain; biasing the memory cell in the linear region; connecting a load and a second transistor in series between the voltage supply and ground, wherein a gate of the second transistor is connected to the gate of the first transistor so that current through the second transistor mirrors current through the first transistor; and measuring at a first terminal of the load a voltage that indicates the threshold voltage of the memory cell.
Claim 2
Independent Claim
114 words
A method for reading a threshold voltage of a memory cell, comprising: connecting the memory cell, a cascoding device, and a first transistor in series between a voltage supply and ground, wherein the first transistor has a gate coupled to its drain; biasing the memory cell in the linear region; connecting a load and a second transistor in series between the voltage supply and ground, wherein a gate of the second transistor is connected to the gate of the first transistor so that current through the second transistor mirrors current through the first transistor; and measuring at a first terminal of the load a voltage that indicates the threshold voltage of the memory cell.
Claim 3
Dependent Claim
77 words
The method of claim 1, wherein measuring the voltage at the first terminal of the load comprises: generating a reference signal which indicates the threshold voltage of a reference cell which has the same structure as the memory cell; connecting the first terminal of the load to a first input terminal of a difference amplifier; applying the reference signal to a second input terminal of the difference amplifier; and measuring the output voltage of the difference amplifier.
Claim 4
Dependent Claim
111 words
The method of claim 2, wherein generating the reference signal comprises: connecting the reference cell, a second cascoding device, and a third transistor in series between the voltage supply and ground, wherein the third transistor has a gate coupled to its drain; biasing the reference cell in the linear region; and connecting a second load and a fourth transistor in series between the voltage supply and ground, wherein a gate of the fourth transistor is connected to the gate of the third transistor so that current through the fourth transistor mirrors current through the third transistor, wherein a voltage at a first terminal of the second load indicates the reference signal.
Claim 5
Independent Claim
106 words
A method for reading a threshold voltage of a memory cell, comprising: coupling a drain/source of the memory cell through a high impedance load to a reference voltage; applying a bias voltage to a control gate of the memory cell; ramping a voltage of a source/drain of the memory cell from the reference voltage to the bias voltage, wherein the ramping is done at a rate which initially operates the memory cell in the linear region and prevents channel hot electrons from disturbing the threshold voltage of the memory cell; and sensing the voltage at the drain/source to determine the threshold voltage of the memory cell.
Claim 6
Independent Claim
106 words
A method for reading a threshold voltage of a memory cell, comprising: coupling a drain/source of the memory cell through a high impedance load to a reference voltage; applying a bias voltage to a control gate of the memory cell; ramping a voltage of a source/drain of the memory cell from the reference voltage to the bias voltage, wherein the ramping is done at a rate which initially operates the memory cell in the linear region and prevents channel hot electrons from disturbing the threshold voltage of the memory cell; and sensing the voltage at the drain/source to determine the threshold voltage of the memory cell.
Claim 7
Dependent Claim
34 words
The method of claim 4, further comprising applying the reference voltage to the source/drain of the memory cell for a time while applying the bias voltage to the control gate and before beginning ramping.
Claim 8
Dependent Claim
69 words
The method of claim 4, wherein sensing the voltage at the drain/source further comprises: generating a reference signal which indicates the threshold voltage of a reference cell having the same structure as the memory cell; connecting the drain/source to a first input terminal of a difference amplifier; applying the reference signal to a second input terminal of the difference amplifier; and measuring the output voltage of the difference amplifier.
Claim 9
Dependent Claim
77 words
The method of claim 6, wherein generating the reference signal comprises: coupling a drain/source of the reference cell through a high impedance load to ground; applying the first bias voltage to a control gate of the reference cell; and ramping a voltage of a source/drain of the reference cell from the reference voltage to the second bias voltage, wherein the drain/source of the reference cell carries the reference signal when the source/drain is at the bias voltage.
Claim 10
Independent Claim
50 words
A method for reading a threshold voltage of a memory cell, comprising: ramping a control gate voltage of the memory cell between a first voltage and a second voltage; sensing when the memory cell transitions between non-conducting and conducting; and reading the control gate voltage when the memory cell transitions.
Claim 11
Independent Claim
50 words
A method for reading a threshold voltage of a memory cell, comprising: ramping a control gate voltage of the memory cell between a first voltage and a second voltage; sensing when the memory cell transitions between non-conducting and conducting; and reading the control gate voltage when the memory cell transitions.
Claim 12
Dependent Claim
14 words
The method of claim 8, wherein ramping comprises changing the control gate voltage continuously.
Claim 13
Dependent Claim
23 words
The method of claim 8, wherein ramping comprises changing the control gate voltage in steps having a size equal to a desired resolution.
Claim 14
Dependent Claim
52 words
The method of claim 8, wherein: the first voltage is lower than a minimum possible threshold voltage for the memory cell; the second voltage is higher than a maximum possible threshold voltage for the memory cell; and ramping comprises increasing the control gate voltage from the first voltage to the second voltage.
Claim 15
Dependent Claim
52 words
The method of claim 8, wherein: the first voltage is higher than a maximum possible threshold voltage for the memory cell; the second voltage is lower than a minimum possible threshold voltage for the memory cell; and ramping comprises decreasing the control gate voltage from the first voltage to the second voltage.
Claim 16
Dependent Claim
67 words
The method of claim 8, further comprising: generating a reference signal which indicates the threshold voltage of a reference cell having the same structure as the memory cell; applying the sampled and held control gate voltage to a first input terminal of a difference amplifier; applying the reference signal to a second input terminal of the difference amplifier; and measuring the output voltage of the difference amplifier.
Claim 17
Dependent Claim
69 words
The method of claim 13, wherein generating the reference signal comprises: ramping a control gate voltage of the reference cell between the first voltage and the second voltage; sensing when the reference cell transitions between conducting and non-conducting; and sampling and holding the control gate voltage of the reference cell when the reference cell transitions, wherein the control gate voltage when the reference cell transitions is the reference signal.
References Cited (Backward Citations)
US4054864A
Cited
US4057788A
Cited
US4200841A
Cited
US4181980A
Cited
US4318188A
Cited
US4520461A
Cited
US4357685A
Cited
US4627027A
Cited
US5012448A
Cited
US4852063A
Cited
US5168465A
Cited
US4996571A
Cited
US4890259A
Cited
US4989179A
Cited
US5055897A
Cited
US5262984A
Cited
US4935702A
Cited
US5042009A
Cited
US5068827A
Cited
US5163021A
Cited
US5172338B1
Cited
US5172338A
Cited
US5028810A
Cited
US5239500A
Cited
US5126967A
Cited
US5241494A
Cited
US5164915A
Cited
US5258949A
Cited
US5220531A
Cited
US5243239A
Cited
US5394362A
Cited
US5218569A
Cited
US5272669A
Cited
US5257225A
Cited
US5294819A
Cited
US5339270A
Cited
US5430670A
Cited
US5485423A
Cited
US5544099A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
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