US5544099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of writing data into electrically erasable and programmable read only memory cell without disturbance to other cells
Assignee: Renesas Electronics Corp
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Filing: 1995-10-16
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Granted: 1996-08-06
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Expires: 2015-10-16
Abstract
Abstract A floating gate type field effect transistor increases the threshold during an application of a write-in pulse to the control gate electrode thereof so as to inject hot electrons into the floating gate electrode, and the write-in pulse is decayed along a waveform having a gradient smaller than a gradient of a pulse signal assumed to take place in a source/drain region of a non-selected floating gate type field effect transistor sharing the selected word line with the selected floating gate type field effect transistor, thereby preventing the non-selected floating gate type field effect transistor from the gate disturb phenomenon.
Inventors
- 👤 Hideki Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:52
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3427; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
260 words
A method of writing data into a memory cell, comprising steps of: a) preparing a semiconductor non-volatile memory device including a plurality of floating gate type field effect transistors serving as addressable memory cells and grouped into a plurality of sectors, each of said plurality of floating gate type field effect transistors having source and drain regions spaced from each other, a floating gate electrode associated with said source and drain regions and electrically isolated from said source and drain regions and a control gate electrode associated with said source and drain regions and electrically isolated from said floating gate electrode and said source and drain regions, a plurality of word lines shared between said plurality of sectors and selectively connected to control gate electrodes of said plurality of floating gate type field effect transistors, and an addressing system having a row addressing subsystem for selectively supplying a write-in pulse signal to said plurality of word lines; b) increasing said write-in pulse signal on a selected one of said plurality of word lines for writing data into at least one floating gate type field effect transistor of a selected one of said plurality of sectors; and c) decaying said write-in pulse along a waveform having a first gradient smaller than a second gradient of a waveform of a pulse signal applied to one of said source and drain regions forming a part of the floating gate type field effect transistor incorporated in a non-selected one of said sectors and coupled to said selected one of said plurality of word lines.
Claim 2
Independent Claim
260 words
A method of writing data into a memory cell, comprising steps of: a) preparing a semiconductor non-volatile memory device including a plurality of floating gate type field effect transistors serving as addressable memory cells and grouped into a plurality of sectors, each of said plurality of floating gate type field effect transistors having source and drain regions spaced from each other, a floating gate electrode associated with said source and drain regions and electrically isolated from said source and drain regions and a control gate electrode associated with said source and drain regions and electrically isolated from said floating gate electrode and said source and drain regions, a plurality of word lines shared between said plurality of sectors and selectively connected to control gate electrodes of said plurality of floating gate type field effect transistors, and an addressing system having a row addressing subsystem for selectively supplying a write-in pulse signal to said plurality of word lines; b) increasing said write-in pulse signal on a selected one of said plurality of word lines for writing data into at least one floating gate type field effect transistor of a selected one of said plurality of sectors; and c) decaying said write-in pulse along a waveform having a first gradient smaller than a second gradient of a waveform of a pulse signal applied to one of said source and drain regions forming a part of the floating gate type field effect transistor incorporated in a non-selected one of said sectors and coupled to said selected one of said plurality of word lines.
Claim 3
Dependent Claim
30 words
The method as set forth in claim 1, in which said write-in pulse is step-wise decayed, and the stepped waveform is approximated to a linear line having said first gradient.
Claim 4
Dependent Claim
158 words
A write-in method for a semiconductor memory device having impurity regions serving as a source region and a drain region and formed in surface portions of a semiconductor substrate, a floating gate electrode provided on a first gate insulating layer covering said semiconductor substrate between said source region and said drain region and a control gate electrode provided on a second gate insulating layer covering said floating gate electrode, said method comprising steps of: data being written into said semiconductor memory device by applying a signal to said control gate, said signal applied to said control gate electrode and changed from a high potential level to a low potential level being approximated to a linear line, a gradient of said linear line being smaller than a gradient of a transition from said high potential level to said low potential level under a time constant determined by a diffusion capacitance and a resistance of each of said impurity regions.
Claim 5
Dependent Claim
158 words
A write-in method for a semiconductor memory device having impurity regions serving as a source region and a drain region and formed in surface portions of a semiconductor substrate, a floating gate electrode provided on a first gate insulating layer covering said semiconductor substrate between said source region and said drain region and a control gate electrode provided on a second gate insulating layer covering said floating gate electrode, said method comprising steps of: data being written into said semiconductor memory device by applying a signal to said control gate, said signal applied to said control gate electrode and changed from a high potential level to a low potential level being approximated to a linear line, a gradient of said linear line being smaller than a gradient of a transition from said high potential level to said low potential level under a time constant determined by a diffusion capacitance and a resistance of each of said impurity regions.
References Cited (Backward Citations)
US4200841A
Cited
US4520461A
Cited
US4617652A
Cited
US4434478A
Cited
US4460982A
Cited
US4611309A
Cited
US4860258A
Cited
US4966571A
Cited
US5068827A
Cited
US5258949A
Cited
US5257225A
Cited
US5487033A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |