Integrated high voltage distribution and control systems

Claim 1

In an integrated circuit nonvolative memory device comprising an array of nonvolatile addressable memory elements connected to row and column address lines, row decoder circuitry for applying a predetermined logic level potential to a selected row line of the memory array and column circuitry for I/0 addressing of a selected column address line, the improvement comprising: coupling/decoupling means for electrically isolating a selected row line at said predetermined potential from the row decoder circuitry, said means including first and second transistors each having a source, drain and gate, the drain of said second transistor being connected to the row line, the source of said first transistor being connected to the row decoder circuitry, the source of said second transistor and the drain of said first transistor being connected together, means connected to the gate of said first transistor for selectively causing said first transistor to be in a non-conductive state so as to isolate said selected row line from said row decoder circuitry, and means connected to the gate of said second transistor for maintaining said second transistor in a conductive state; and low power high voltage charging means for charging the selected, isolated row line at said predetermined potential to a higher potential while preventing charging of unselected row lines to such higher potential, said means including a third transistor for controlling the application of said higher potential to said isolated row line and a fourth transistor for regulating the condition of said third transistor as a function of the potential of said isolated row line.