Semiconductor memory

Claim 2

A semiconductor memory, comprising: a plurality of memory cells arranged in a row; a word line, operatively connected to said plurality of memory cells, for selecting said memory cells, said word line being switched from a selected state to a non-selected state and from the non-selected state to the selected state; at least one transistor, operatively connected to said word line, for discharging said word line, said at least one transistor having a gate; and means, operatively connected to said at least one transistor for generating a pulse having a predetermined width by detecting when said word line is switched from the selected state to the non-selected state and for turning on said at least one transistor for a predetermined period of time, thereby accelerating the discharge of the word line from the selected state to the non-selected state.

Claim 3

A semiconductor memory according to claim 1, wherein said at least one transistor is connected to a point substantially in the middle of said word line.

Claim 4

A semiconductor memory according to claim 1, further comprising at least one relay buffer operatively connected to said word line, said at least one relay buffer having an input terminal and an output terminal, each said terminal operatively connected to said word line.

Claim 5

A semiconductor memory according to claim 3, wherein said at least one relay buffer is operatively connected to a point substantially in the middle of said word line, and wherein said at least one transistor is operatively connected to said input terminal of said at least one relay buffer.

Claim 6

A semiconductor memory according to claim 4, wherein said means for turning on said at least one transistor comprises: a first control transistor having a gate operatively connected to said output terminal of said at least one relay buffer and said gate of said at least one transistor; a second control transistor operatively connected between said gate of said at least one transistor and a ground potential point, said second control transistor having a gate; and means, operatively connected to said at least one relay buffer, said first control transistor and said second control transistor, for generating a reset signal and a reversed reset signal for the predetermined period when said word line is switched from the selected state to the non-selected state, wherein said gate of said at least one transistor is operatively connected to receive the reset signal, and wherein said gate of said second control transistor is operatively connected to receive the reversed reset signal.

Claim 7

A semiconductor memory according to claim 5, further comprising a third control transistor, operatively connected to an end of said word line and to the reset signal generating means, for discharging said word line, said third control transistor being controlled by the reset signal.

Claim 8

A semiconductor memory, comprising: memory cells arranged in a row; a word line having a selected state and a non-selected state, operatively connected to said memory cells, for selecting said memory cells in accordance with said selected or non-selected state; a transistor, operatively connected to said word line, for discharging said word line; means, operatively connected to said transistor, for generating a pulse having a predetermined width by detecting when said word line is switched from said selected state to said non-selected state and for turning on said transistor for a predetermined period of time, thereby accelerating the discharging of the word line from the selected state to the non-selected state.

Claim 9

A semiconductor memory, comprising: memory cells arranged in a row; a word line having a selected state and a non-selected state, operatively connected to said memory cells, for selecting said memory cells in accordance with said selected or non-selected state; a transistor, operatively connected to said word line, for discharging said word line; means, operatively connected to said transistor, for generating a pulse having a predetermined width by detecting when said word line is switched from said selected state to said non-selected state and for turning on said transistor for a predetermined period of time, thereby accelerating the discharging of the word line from the selected state to the non-selected state.

Claim 10

A semiconductor memory, according to claim 7, wherein said transistor is connected to a point substantially in the middle of said word line.

Claim 11

A semiconductor memory, according to claim 7, further comprising a relay buffer operatively connected to said word line, having an input and output terminal operatively connected to said word line.

Claim 12

A semiconductor memory according to claim 9, wherein said relay buffer is operatively connected to a point substantially in the middle of said word line, and wherein said transistor is operatively connected to said input terminal of said relay buffer.

Claim 13

A semiconductor memory according to claim 10, wherein said transistor has a gate and wherein said means for turning on said transistor comprises: a first control transistor having a gate operatively connected to said output terminal of said relay buffer and said gate of said transistor; a second control transistor having a gate, operatively connected between said gate of said transistor and a ground potential point; and means, operatively connected to said relay buffer, said first control transistor, and said second control transistor, for generating a reset signal and a reversed reset signal for the predetermined period when said state of said word line is switched from said selected state to said non-selected state, wherein said gate of said transistor is operatively connected to receive the reset signal, and wherein said gate of said second control transistor is operatively connected to receive the reversed reset signal.

Claim 14

A semiconductor memory according to claim 11, further comprising a third control transistor, operatively connected to an end of said word line and to said reset signal generating means, for discharging said word lines in dependence upon the reset signal.

Claim 15

A semiconductor memory, operatively connected to receive address input signals, according to claim 1, wherein said generating means generates said pulse by detecting a transition in the address input signals.