US4280198A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuit arrangement for controlling an integrated semiconductor memory
Assignee: International Business Machines Corp
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Filing: 1979-12-07
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Granted: 1981-07-21
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Expires: 1999-12-07
Abstract
Abstract In integrated semiconductor memory cell arrangements, particularly integrated semiconductor memory cell arrangements using merged transistor logic configurations, line capacitances are discharged before accessing to reduce access time and power consumption. Individual bit line transistor switching means are coupled to each bit line to provide a discharge path for the line capacitances associated therewith. Common transistor switching means are coupled to each individual bit line transistor switching means to commonly discharge the individual discharge currents received from each individual bit line transistor switching means. Individual word line transistor switching means are also connected to respective word lines to distribute the current passing through the common transistor switching means to the respective word lines. The discharge circuit arrangement permits minimum-area bit line and word line transistor switching means.
Inventors
- 👤 Klaus Heuber
- 👤 Siegfried K. Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402; G11C11/4026; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/414; G11C11/416
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
110 words
In a method of controlling a semiconductor memory of arrayed memory cells including arrayed memory cells arranged in merged transistor logic with said cells coupled at intersections of word and bit lines and selected via word line drivers and decoders, the improvement residing in discharging the line capacitances for reducing the access time and power consumption of said memory cells, comprising the steps of, discharging said line capacitance before cell selection by causing said line capacitances to discharge through line control means coupled to respective ones of the bit lines or word lines associated with each cell and then through a common control means common to all line control means.
Claim 2
Dependent Claim
110 words
In a method of controlling a semiconductor memory of arrayed memory cells including arrayed memory cells arranged in merged transistor logic with said cells coupled at intersections of word and bit lines and selected via word line drivers and decoders, the improvement residing in discharging the line capacitances for reducing the access time and power consumption of said memory cells, comprising the steps of, discharging said line capacitance before cell selection by causing said line capacitances to discharge through line control means coupled to respective ones of the bit lines or word lines associated with each cell and then through a common control means common to all line control means.
Claim 3
Dependent Claim
35 words
The method of claim 1 wherein at least a portion of the current discharged through said common control means is discharged through line control means coupled to the said bit lines associated with each cell.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein the current discharged through said common control means is discharged to a reference potential.
Claim 5
Dependent Claim
133 words
In memory arrays of semiconductor memory cells including arrays of semiconductor memory cells arranged in merged transistor logic, said cells coupled at the intersections of word lines and bit lines and selected via word line drivers and decoders, the improvement residing in discharging line capacitances before accessing for reducing the access time and power consumption of said memory cells, comprising; individual control means respectively coupled to each bit line for discharging line capacitances; common control means coupled to each individual control means for discharging in common all of the said line capacitances discharged through said individual control means; and discharge control means coupled to the said individual control means and said common control means to concurrently apply discharge control signals thereto to cause said line capacitances to discharge before each cell selection operation.
Claim 6
Dependent Claim
133 words
In memory arrays of semiconductor memory cells including arrays of semiconductor memory cells arranged in merged transistor logic, said cells coupled at the intersections of word lines and bit lines and selected via word line drivers and decoders, the improvement residing in discharging line capacitances before accessing for reducing the access time and power consumption of said memory cells, comprising; individual control means respectively coupled to each bit line for discharging line capacitances; common control means coupled to each individual control means for discharging in common all of the said line capacitances discharged through said individual control means; and discharge control means coupled to the said individual control means and said common control means to concurrently apply discharge control signals thereto to cause said line capacitances to discharge before each cell selection operation.
Claim 7
Dependent Claim
56 words
In the memory arrays as set forth in claim 4 including further control means coupled between said common control means and respective ones of said word lines to cause at least a portion of the discharge current passing through said common control means to be directed to respective ones of said word lines for distribution thereover.
Claim 8
Dependent Claim
48 words
In the memory arrays as set forth in claim 5 wherein said discharge control means coupled to the said individual control means and common control means comprises control logic means coupled to receive cell selection signals and initiate said discharge control signals prior to initiating cell selection signals.
Claim 9
Dependent Claim
24 words
In the memory arrays as set forth in claim 6 wherein said common control means includes a common switching transistor with collector-emitter voltage stabilization.
Claim 10
Dependent Claim
27 words
In the memory arrays as set forth in claim 6 wherein the individual control means and the further control means each comprise transistors which are minimum-area transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-20 | 1985-01-19 | 1985-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-20 | 1989-01-19 | 1989-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-20 | 1993-01-19 | 1993-07-21 | $7700.00 | Window Closed / Lapsed |