Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
249 words
In a method for producing complementary MOS transistors and complementary bipolar transistors on the same semiconductor wafer, which includes producing buried zones of differing conductivity, producing n-doped and p-doped wells for corresponding transistors, and producing field oxide regions and insulated gate electrodes of the MOS transistors, the improvement which comprises: after the production of the field oxide regions, producing highly doped n-regions extending from a surface of the semiconductor wafer and reaching to a given buried n-doped zone with a first mask for producing a collector zone of an npn transistor and a base zone of a pnp transistor; after the production of the insulated gate electrodes, applying a first silicon layer over the entire surface and doping the first silicon layer with p-atoms; applying an auxiliary layer on the first silicon layer over the entire surface; structuring the auxiliary layer and the first silicon layer with a second mask; simultaneously producing a base contact zone of the npn transistor, source and drain zones of a p-MOS transistor, and a collector zone and an emitter zone of the pnp transistor, by diffusion out from the structured first silicon layer; laterally insulating the first silicon layer, and producing, doping with n-atoms, and structuring a second silicon layer with a mask; and simultaneously producing an emitter zone and a collector terminal zone of the npn transistor, a base terminal of the pnp transistor, and source and drain zones of an n-MOS transistor, by diffusion out from the structured second silicon layer.
Claim 2
Dependent Claim
249 words
In a method for producing complementary MOS transistors and complementary bipolar transistors on the same semiconductor wafer, which includes producing buried zones of differing conductivity, producing n-doped and p-doped wells for corresponding transistors, and producing field oxide regions and insulated gate electrodes of the MOS transistors, the improvement which comprises: after the production of the field oxide regions, producing highly doped n-regions extending from a surface of the semiconductor wafer and reaching to a given buried n-doped zone with a first mask for producing a collector zone of an npn transistor and a base zone of a pnp transistor; after the production of the insulated gate electrodes, applying a first silicon layer over the entire surface and doping the first silicon layer with p-atoms; applying an auxiliary layer on the first silicon layer over the entire surface; structuring the auxiliary layer and the first silicon layer with a second mask; simultaneously producing a base contact zone of the npn transistor, source and drain zones of a p-MOS transistor, and a collector zone and an emitter zone of the pnp transistor, by diffusion out from the structured first silicon layer; laterally insulating the first silicon layer, and producing, doping with n-atoms, and structuring a second silicon layer with a mask; and simultaneously producing an emitter zone and a collector terminal zone of the npn transistor, a base terminal of the pnp transistor, and source and drain zones of an n-MOS transistor, by diffusion out from the structured second silicon layer.
Claim 3
Dependent Claim
29 words
The method according to claim 1, which comprises applying an amorphous silicon layer as the first silicon layer, and recrystallizing the amorphous silicon layer after the doping with p-atoms.
Claim 4
Dependent Claim
32 words
The method according to claim 1, which comprises doping over the entire surface with p-atoms, after the structuring of the first silicon layer, to produce a base zone for the npn transistor.
Claim 5
Dependent Claim
34 words
The method according to claim 1, which comprises low doping the zones of the semiconductor wafer intended for the source and drain regions of the MOS transistors, before the first silicon layer is applied.
Claim 6
Dependent Claim
58 words
The method according to claim 1, which comprises doping the first silicon layer in nonmasked regions, correspondingly doping the masked regions with a second p-conductive material with a lower doping than is intended for the nonmasked regions, in a preceding step, and exposing the masked regions after the doping of the nonmasked regions of the first silicon layer.
Claim 7
Dependent Claim
78 words
The method according to claim 1, which comprises during the structuring of the first silicon layer, forming a first capacitance electrode; placing lateral insulation ribs on the first silicon layer after its structuring; forming a further structuring mask on the first capacitance electrode for further structuring of the auxiliary layer; partially removing the auxiliary layer; and applying, doping, and structuring the second silicon layer to form a second capacitance electrode, after the removal of the further structuring mask.
Claim 8
Dependent Claim
39 words
The method according to claim 1, which comprises insulating the first and second silicon layers from one another and from the gate electrodes of the MOS transistors, and exposing and siliconizing surfaces in the first and second silicon layers.