EP0325181A2
Expired / Lapsed
EP
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A method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide
Assignee: National Semiconductor Corp
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Filing: 1989-01-14
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Granted: —
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Expires: 2009-01-14
Abstract
Abstract A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.
Inventors
- 👤 Michael P. Brassington
- 👤 Reda R. Razouk
- 👤 Monir H. El-Diwany
- 👤 Prateep Tuntasood
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 14:57
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
120 words
A method of making a polysilicon emitter simultaneously with a polysilicon gate in a semiconductor device comprising the steps of; growing a thin layer of gate oxide on emitter and gate regions of a silicon substrate; depositing a thin layer of polysilicon on the gate oxide layer; removing the thin polysilicon layer from the emitter region of the silicon substrate; removing the gate oxide layer from the emitter region of the silicon substrate; depositing a thick layer of polysilicon on the emitter and gate regions of the silicon substrate; masking the emitter and gate regions for forming a respective emitter and gate; and simultaneously etching the polysilicon from the emitter and gate regions for forming the respective emitter and gate.
Claim 2
Independent Claim
120 words
A method of making a polysilicon emitter simultaneously with a polysilicon gate in a semiconductor device comprising the steps of; growing a thin layer of gate oxide on emitter and gate regions of a silicon substrate; depositing a thin layer of polysilicon on the gate oxide layer; removing the thin polysilicon layer from the emitter region of the silicon substrate; removing the gate oxide layer from the emitter region of the silicon substrate; depositing a thick layer of polysilicon on the emitter and gate regions of the silicon substrate; masking the emitter and gate regions for forming a respective emitter and gate; and simultaneously etching the polysilicon from the emitter and gate regions for forming the respective emitter and gate.
Claim 3
Dependent Claim
75 words
The method according to claim 1 wherein the polysilicon layer removing step comprises the steps of; depositing a photoresist layer as a blanket coating above the thin polysilicon layer; developing the photoresist layer for forming an opening in the photoresist layer for exposing the portion of the polysilicon layer above the emitter region; and etching the exposed portion of the polysilicon layer for exposing the portion of the gate oxide layer above the emitter region.
Claim 4
Dependent Claim
37 words
The method according to claim 2 wherein the gate oxide layer removing step comprises the steps of: retaining the photoresist layer; and etching the exposed portion of the gate oxide layer in a buffered oxide etching solution.
Claim 5
Dependent Claim
49 words
The method according to claim 3 wherein the gate oxide growing step comprises the step of: growing a layer of silicon dioxide on emitter and gate regions of the silicon substrate, the silicon dioxide having a thickness in the range of from approximately 150 angstroms to approximately 300 angstroms.
Claim 6
Dependent Claim
32 words
The method according to claim 4 wherein the polysilicon layer depositing step comprises the step of depositing a polysilicon layer to a thickness of from approximately 500 angstroms to approximately 1000 angstroms.
Claim 7
Dependent Claim
39 words
The method according to claim 5 further comprising the steps of: depositing a conformal oxide layer as a blanket coating over the silicon substrate; and anisotropically etching the conformal layer from the bipolar region and from the MOS region.
Claim 8
Independent Claim
266 words
A method of simultaneously making a polysilicon emitter with a polysilicon gate in a semiconductor device comprising the steps of: forming a bipolar region in a silicon substrate for a bipolar device, the bipolar region having a first region, termed a collector region, and a second region, the first and second regions being separated by a first field oxide region: forming a MOS region in the silicon substrate for a MOS device, the MOS region being separate from the bipolar region by a second field oxide region; forming a thin gate oxide layer on the bipolar region and on the MOS region; forming a thin polysilicon layer on the bipolar region and on the MOS region; removing the thin polysilicon layer from the second region; removing the thin gate oxide layer from the second region; depositing a thick polysilicon layer on the bipolar region and on the MOS region; masking a portion of the second region for forming an emitter; masking a portion of the MOS region for forming a gate; simultaneously etching the polysilicon from the bipolar region and from the MOS region other than from the masked portions of the bipolar region and the MOS region; removing the thin gate oxide layer from the collector region; doping the collector region and the MOS region to a first conductivity type; doping the second region to a conductivity type opposite the conductivity type of the collector region; depositing a conformal oxide layer on the bipolar region and on the MOS region; and anisotropically etching the conformal layer from the bipolar region and from the MOS region.
Claim 9
Independent Claim
266 words
A method of simultaneously making a polysilicon emitter with a polysilicon gate in a semiconductor device comprising the steps of: forming a bipolar region in a silicon substrate for a bipolar device, the bipolar region having a first region, termed a collector region, and a second region, the first and second regions being separated by a first field oxide region: forming a MOS region in the silicon substrate for a MOS device, the MOS region being separate from the bipolar region by a second field oxide region; forming a thin gate oxide layer on the bipolar region and on the MOS region; forming a thin polysilicon layer on the bipolar region and on the MOS region; removing the thin polysilicon layer from the second region; removing the thin gate oxide layer from the second region; depositing a thick polysilicon layer on the bipolar region and on the MOS region; masking a portion of the second region for forming an emitter; masking a portion of the MOS region for forming a gate; simultaneously etching the polysilicon from the bipolar region and from the MOS region other than from the masked portions of the bipolar region and the MOS region; removing the thin gate oxide layer from the collector region; doping the collector region and the MOS region to a first conductivity type; doping the second region to a conductivity type opposite the conductivity type of the collector region; depositing a conformal oxide layer on the bipolar region and on the MOS region; and anisotropically etching the conformal layer from the bipolar region and from the MOS region.
Claim 10
Dependent Claim
75 words
The method according to claim 7 wherein the polysilicon layer removing step comprises the steps of: depositing a photoresist layer as a blanket coating over the thin polysilicon layer; developing the photoresist layer for forming an opening in the photoresist layer for exposing the portion of the polysilicon layer above the emitter region; and etching the exposed portion of the polysilicon layer for exposing the portion of the gate oxide layer above the emitter region.
Claim 11
Dependent Claim
37 words
The method according to claim 8 wherein the gate oxide layer removing step comprises the steps of: retaining the photoresist layer; and etching the exposed portion of the gate oxide layer in a buffered oxide etching solution.
Claim 12
Dependent Claim
49 words
The method according to claim 9 wherein the gate oxide growing step comprises the step of: growing a layer of silicon dioxide on emitter and gate regions of the silicon substrate, the silicon dioxide having a thickness in the range of from approximately 150 angstroms to approximately 300 angstroms.
Claim 13
Dependent Claim
32 words
The method according to claim 10 wherein the polysilicon layer depositing step comprises the step of depositing a polysilicon layer to a thickness of from approximately 500 angstroms to approximately 1000 angstroms.
Claim 14
Dependent Claim
205 words
A semiconductor device formed in a single silicon substrate comprising: a bipolar transistor, including a collector region formed of a semiconductor material having a first conductivity type; a base region electrically coupled to the collector region, the base region being formed of a semiconductor material having a conductivity type opposite the conductivity type of the semiconductor material forming the collector region; and a polycrystalline silicon layer electrically contacting the base region for forming an emitter, the polycrystalline silicon layer being doped with an impurity having the same conductivity type as the semiconductor material forming the collector region; an MOS transistor, including: a source region formed of a semiconductor material having a first conductivity type; a drain region formed of a semiconductor material having the same conductivity type as the semiconductor material forming the source region, the drain region being spaced apart from the source region; a thin gate oxide layer disposed over the silicon substrate between the source region and the gate region; a polycrystalline silicon layer disposed over the gate oxide layer for forming a gate electrode, the polycrystalline silicon layer being doped with an impurity having a conductivity type opposite the conductivity type of the semiconductor material forming the source and drain regions.
Claim 15
Dependent Claim
205 words
A semiconductor device formed in a single silicon substrate comprising: a bipolar transistor, including a collector region formed of a semiconductor material having a first conductivity type; a base region electrically coupled to the collector region, the base region being formed of a semiconductor material having a conductivity type opposite the conductivity type of the semiconductor material forming the collector region; and a polycrystalline silicon layer electrically contacting the base region for forming an emitter, the polycrystalline silicon layer being doped with an impurity having the same conductivity type as the semiconductor material forming the collector region; an MOS transistor, including: a source region formed of a semiconductor material having a first conductivity type; a drain region formed of a semiconductor material having the same conductivity type as the semiconductor material forming the source region, the drain region being spaced apart from the source region; a thin gate oxide layer disposed over the silicon substrate between the source region and the gate region; a polycrystalline silicon layer disposed over the gate oxide layer for forming a gate electrode, the polycrystalline silicon layer being doped with an impurity having a conductivity type opposite the conductivity type of the semiconductor material forming the source and drain regions.
Claim 16
Dependent Claim
26 words
The device according to claim 12 wherein the gate oxide layer has a thickness in the range of from approximately 150 angstroms to approximateiy 300 angstroms.
Claim 17
Dependent Claim
28 words
The device according to claim 13 wherein the polysilicon layer forming the emitter has a thickness in the range of from approximately 2200 angstroms to approximately 2800 angstroms.
Claim 18
Dependent Claim
26 words
The device according to claim 14 wherein the polycrystalline silicon layer has a thickness in the range of from approximately 2700 angstroms to approximately 3800 angstroms.
References Cited (Backward Citations)
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