Microprocessor with externally controllable power management

Claim 2

A microprocessor device having external interface terminals, comprising: a plurality of subcircuits including at least one pipeline subcircuit to execute instructions for data processing; clock pulse generator circuitry which is an internal part of said microprocessor device, wherein said clock pulse generator circuitry is coupled to said plurality of subcircuits to supply clock pulses thereto; detector circuitry which is coupled to one of said external interface terminals to detect a control signal at said one external interface terminal from an external source; and circuitry which is coupled to said detector circuitry to respond to said control signal by disabling the supply of said clock pulses by said clock pulse generator circuitry to said at least one pipeline subcircuit, after completion of execution of an instruction currently in said at least one pipeline subcircuit, and to generate a signal at another of said external interface terminals, indicating disablement of the supply of said clock pulses to said at least one pipeline subcircuit.

Claim 3

The microprocessor device of claim 1 wherein said disabling circuitry comprises circuitry to maintain the clock pulses to said at least one pipeline subcircuit in a predetermined state.

Claim 4

The microprocessor device of claim 1 wherein said at least one pipeline subcircuit comprises a microcode memory and an instruction execution unit.

Claim 5

The microprocessor device of claim 1 and further comprising circuitry to resume enablement of said clock pulse generator circuitry to supply said clock pulses to said at least one pipeline subcircuit responsive to de-assertion of said control signal.

Claim 6

The microprocessor device of claim 1 and further comprising an exception processor is coupled to circuitry to generate an interrupt responsive to detecting assertion of said control signal and to supply said interrupt to said exception processor, said exception processor executing a power-down microcode routine in response to said interrupt.

Claim 7

A computer comprising: a microprocessor device having interface terminals, said microprocessor comprising; a plurality of subcircuits including at least one pipeline subcircuit to execute instructions for data processing; clock generator circuitry which is an internal part of said microprocessor device coupled to a first one of said interface terminals for receiving a clock signal from an external source and to generate and supply clock pulses to said plurality of subcircuits; detector circuitry which is coupled to said computer to detect assertion of a control signal by said computer; and circuitry which is coupled to said detector circuitry to respond to said control signal by disabling, independently of said clock signal from said external source, the supply of clock pulses from said clock generator circuitry to said at least one pipeline subcircuit, after completion of execution of an instruction currently in said at least one pipeline subcircuit and to generate a signal from said microprocessor device to said computer indicating disablement of the supply of said clock pulses to said at least one pipeline subcircuit; said computer also including: circuitry to detect conditions for suspending operations of said at least one pipeline subcircuit and to assert said control signal responsive thereto; and circuitry to detect conditions for resuming operation of said at least one pipeline subcircuit and to de-assert said control signal responsive thereto.

Claim 8

A computer comprising: a microprocessor device having interface terminals, said microprocessor comprising; a plurality of subcircuits including at least one pipeline subcircuit to execute instructions for data processing; clock generator circuitry which is an internal part of said microprocessor device coupled to a first one of said interface terminals for receiving a clock signal from an external source and to generate and supply clock pulses to said plurality of subcircuits; detector circuitry which is coupled to said computer to detect assertion of a control signal by said computer; and circuitry which is coupled to said detector circuitry to respond to said control signal by disabling, independently of said clock signal from said external source, the supply of clock pulses from said clock generator circuitry to said at least one pipeline subcircuit, after completion of execution of an instruction currently in said at least one pipeline subcircuit and to generate a signal from said microprocessor device to said computer indicating disablement of the supply of said clock pulses to said at least one pipeline subcircuit; said computer also including: circuitry to detect conditions for suspending operations of said at least one pipeline subcircuit and to assert said control signal responsive thereto; and circuitry to detect conditions for resuming operation of said at least one pipeline subcircuit and to de-assert said control signal responsive thereto.

Claim 9

The computer of claim 6 and further comprising a display for outputting data.

Claim 10

The computer of claim 7 and further comprising circuitry for disabling said display.

Claim 11

The computer of claim 7 and further comprising a coprocessor which is coupled to said microprocessor device to assert a busy signal to said microprocessor device during operation of said coprocessor, and wherein said circuitry which is coupled to said detector circuitry to respond to said control signal by disabling the supply of clock pulses from said clock generator circuitry to said at least one pipeline circuit is inhibited during assertion of said busy signal.

Claim 12

The computer of claim 6 wherein said processing unit further comprises circuitry operable to resume supply by said clock generator circuitry of the clock pulses to said at least one pipeline subcircuit responsive to de-assertion of said control signal.

Claim 15

The method of claim 11 wherein said disabling step comprises the step of maintaining the supply of clock pulses to said at least one pipeline instruction execution subcircuit in a predetermined state.

Claim 16

The method of claim 11 and further comprising the step of resuming the supply of clock pulses generated internally of said microprocessor device to said at least one pipeline instruction execution subcircuit responsive to de-assertion of said control signal.

Claim 17

The method of claim 11 and further comprising the step of causing the microprocessor device to generate an interrupt responsive to detecting said control signal and to execute a power-down microcode routine in response to said interrupt.