US4796235A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Write protect mechanism for non-volatile memory
Assignee: NXP USA Inc
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Filing: 1987-07-22
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Granted: 1989-01-03
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Expires: 2007-07-22
Abstract
Abstract A write protect mechanism for a programmable read-only memory prevents writes to the PROM unless a protect register contains predetermined information. The protect register is itself a write protected control register. The predetermined information cannot be written into the protect register except during a short, predetermined period after the occurrence of an event such as a reset. The protect register may be written to with information other than the predetermined information at any time. The preferred embodiment comprises a single-chip microcomputer with on-board electrically-erasable programmable read-only memory which is write protected in several, separate blocks.
Inventors
- 👤 Robert W. Sparks
- 👤 Brian F. Wilkie
- 👤 George G. Grimmer, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:40
CPC Classifications
G; G06; G06F; G06F21/00; G06F21/70; G06F21/78; G06F21/79; G06F12/00; G06F12/14; G06F12/1458; G06F12/1466; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G11C16/22
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
122 words
In a system comprising a PROM, a write protect register, clock means for providing a clock signal and write protect means for allowing writes to the PROM if and only if the write protect register contains predetermined data, a write protect control apparatus comprising: timer means responsive to the clock signal and to an external event to generate a timeout signal a predetermined number of cycles of the clock signal after the occurrence of the external event; and register protect means responsive to the external event and to the timeout signal for allowing the writing of the predetermined data into the write protect register only in the period between the occurrence of the external event and the generation of the timeout signal.
Claim 2
Dependent Claim
122 words
In a system comprising a PROM, a write protect register, clock means for providing a clock signal and write protect means for allowing writes to the PROM if and only if the write protect register contains predetermined data, a write protect control apparatus comprising: timer means responsive to the clock signal and to an external event to generate a timeout signal a predetermined number of cycles of the clock signal after the occurrence of the external event; and register protect means responsive to the external event and to the timeout signal for allowing the writing of the predetermined data into the write protect register only in the period between the occurrence of the external event and the generation of the timeout signal.
Claim 3
Dependent Claim
26 words
An apparatus according to claim 1 wherein: said with protect register means is responsive to said external event to store data other than said, predetermined data.
Claim 4
Dependent Claim
13 words
An apparatus according to claim 2 wherein: said external event is a reset.
Claim 5
Dependent Claim
51 words
An apparatus according to claim 1 further comprising: configure means for configuring the PROM for programming or for reading only, said write protect means is responsive to said configure means to allow access to the PROM regardless of said write protect register means if the PROM is configured for reading only.
Claim 6
Dependent Claim
20 words
An apparatus according to claim 1 wherein said write protect means further comprises: means for selectably disabling an address decoder.
Claim 7
Dependent Claim
76 words
An apparatus according to claim 1 wherein: said write protect register further comprises a plurality of bit storage locations; the PROM comprises a number of separately write protectable portions equal to the number of bit storage locations in said protect register; and said write protect means further comprises means for allowing writes to each of said separately write protectable portions only if a predetermined one of said bit storage locations is in a first, predetermined state.
Claim 8
Dependent Claim
94 words
An apparatus according to claim 6 wherein said timer means further comprises: first means for generating a first logic signal which changes from a first state to a second state at a predetermined time after said external event; and second means for allowing said bit storage locations of said write protect register to be placed in said first, predetermined state only while said first logic signal is in said first state, said second means allowing said bit storage locations to be placed in a state other than said first, predetermined state at any time.
Claim 9
Dependent Claim
169 words
A data processing system comprising: CPU means for executing instructions; reset means for resetting the system in response to an external event; clock means for generating a clock signal and a timeout signal, said time-out signal changes from a first state to a second state a predetermined time after the system is reset by said reset means; and PROM means for storing data, said PROM means being readable and writable by said CPU means under control of said instructions; the data processing system being characterized by a write protect apparatus comprising: protect register means for storing information; write protect means for preventing said CPU means from writing to said PROM means, said write protect means being responsive to predetermined information stored in said protect register means to allow said CPU means to write to said PROM means; and means responsive to said time-out signal to allow said CPU means to store said predetermined information in said protect register means only if said time-out signal is in said first state.
Claim 10
Dependent Claim
169 words
A data processing system comprising: CPU means for executing instructions; reset means for resetting the system in response to an external event; clock means for generating a clock signal and a timeout signal, said time-out signal changes from a first state to a second state a predetermined time after the system is reset by said reset means; and PROM means for storing data, said PROM means being readable and writable by said CPU means under control of said instructions; the data processing system being characterized by a write protect apparatus comprising: protect register means for storing information; write protect means for preventing said CPU means from writing to said PROM means, said write protect means being responsive to predetermined information stored in said protect register means to allow said CPU means to write to said PROM means; and means responsive to said time-out signal to allow said CPU means to store said predetermined information in said protect register means only if said time-out signal is in said first state.
Claim 11
Dependent Claim
27 words
A data processing system according to claim 8 wherein: said protect register means is responsive to said reset means to store information other than said predetermined information.
Claim 12
Dependent Claim
35 words
A data processing system according to claim 8 wherein: said CPU means is able to store information other than said predetermindd information in said protect register means regardless of the state of said time-out signal.
Claim 13
Dependent Claim
22 words
A data processing system according to claim 8 wherein said write protect means further comprises: means for selectably disabling an address decoder.
Claim 14
Dependent Claim
59 words
A data processing system according to claim 11 further comprising: configure means for configuring said PROM means for programming or for reading only, said write protect means is responsive to said configure means to allow access to said PROM means regardless of the information stored in said protect register means if said PROM means is configured for reading only.
Claim 15
Dependent Claim
113 words
In a system comprising a PROM, a write protect register, clock means for providing a clock signal and write protect means for allowing writes to the PROM if and only if the write protect register contains predetermined data, a method of protecting the PROM from inadvertent writes comprising the steps of: responding to an external event and to the clock signal by generating a timeout signal a predetermined number of cycles of the clock signal after the occurrence of the external event; and allowing the predetermined data to be written into the write protect register only during the period between the occurrence of the external event and the generation of the timeout signal.
Claim 16
Dependent Claim
113 words
In a system comprising a PROM, a write protect register, clock means for providing a clock signal and write protect means for allowing writes to the PROM if and only if the write protect register contains predetermined data, a method of protecting the PROM from inadvertent writes comprising the steps of: responding to an external event and to the clock signal by generating a timeout signal a predetermined number of cycles of the clock signal after the occurrence of the external event; and allowing the predetermined data to be written into the write protect register only during the period between the occurrence of the external event and the generation of the timeout signal.
Claim 17
Dependent Claim
32 words
A method according to claim 13 further comprising the step of: storing data other than said predetermined data in said write protect register in response to the occurrence of said external event.
Claim 18
Dependent Claim
13 words
A method according to claim 14 wherein: said external event is a reset.
Claim 19
Dependent Claim
25 words
A method according to claim 13 wherein said step of allowing writes to the PROM further comprises the step of: selectably disabling an address decoder.
Claim 20
Dependent Claim
43 words
A method according to claim 16 further comprising the steps of: configuring the PROM for programming or for reading only; and allowing access to the PROM regardless of the data stored in said protect register if the PROM is configured for reading only.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-03 | 1992-07-04 | 1993-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-03 | 1996-07-04 | 1997-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-03 | 2000-07-04 | 2001-01-03 | $7700.00 | Window Closed / Lapsed |