US4573117A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus in a data processor for selectively disabling a power-down instruction
Assignee: MOTORLA Inc A DE CORP
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Filing: 1983-11-07
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Granted: 1986-02-25
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Expires: 2003-11-07
Abstract
Abstract A method for allowing the user of a data processor having a power-down instruction to selectively disable the power-down instruction. In the preferred circuit, the user stores a special code in a control register indicating that the power-down instruction is to be disabled. Upon a power-down instruction being subsequently executed, the processor is precluded by the code from turning off the oscillator which provides the system clocks. The processor thus proceeds to the next instruction as if the power-down instruction were a "no-operation" instruction.
Inventors
- 👤 Joel F. Boney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:51
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
206 words
In a data processor comprising: oscillator means for providing a periodic clock signal except in response to receiving a power-down signal; reset means for providing a reset signal in response to a predetermined condition; and instruction execution control means, operative in synchronism with said clock signal, for receiving each of a plurality of different instructions comprising an instruction stream, and, in response to receiving a predetermined power-down instruction in said instruction stream, providing said power-down signal to said oscillator means to terminate said clock signal until said reset means next provides said reset signal, said instruction execution control means proceeding to a next instruction in said instruction stream only upon resumption of said clock signal; a circuit for selectively disabling said power-down instruction, comprising: control register means for storing a predetermined control code in response to said instruction execution control means receiving a different predetermined one of said instructions in said instruction stream; and logic means responsive to said control code being stored in said control register means, for preventing said instruction execution control means from providing said power-down signal to said oscillator in response to said power-down instruction, whereby said instruction execution control means will simply proceed to said next instruction in said instruction stream.
Claim 2
Dependent Claim
206 words
In a data processor comprising: oscillator means for providing a periodic clock signal except in response to receiving a power-down signal; reset means for providing a reset signal in response to a predetermined condition; and instruction execution control means, operative in synchronism with said clock signal, for receiving each of a plurality of different instructions comprising an instruction stream, and, in response to receiving a predetermined power-down instruction in said instruction stream, providing said power-down signal to said oscillator means to terminate said clock signal until said reset means next provides said reset signal, said instruction execution control means proceeding to a next instruction in said instruction stream only upon resumption of said clock signal; a circuit for selectively disabling said power-down instruction, comprising: control register means for storing a predetermined control code in response to said instruction execution control means receiving a different predetermined one of said instructions in said instruction stream; and logic means responsive to said control code being stored in said control register means, for preventing said instruction execution control means from providing said power-down signal to said oscillator in response to said power-down instruction, whereby said instruction execution control means will simply proceed to said next instruction in said instruction stream.
Claim 3
Dependent Claim
110 words
The data processor of claim 1 further comprising: data register means for storing said predetermined code in response to said instruction execution control means receiving a third predetermined one of said instructions is said instruction stream, and for providing said predetermined control code in response to said instruction execution control means receiving said different predetermined one of said instructions in said instruction stream; and wherein said control register means are further characterized as receiving said predetermined control code from said data register and then storing said received predetermined control code in response to said instruction execution control means receiving said different predetermined one of said instructions in said instruction stream.
Claim 4
Dependent Claim
83 words
The data processor of claim 1 wherein said instruction execution control means includes latch means for asserting a disable signal in response to said instruction execution control means receiving said power-down instruction, and for negating said disable signal in response to said reset signal; and wherein said logic means includes gate means for providing said power-down signal to said oscillator in response to the assertion of said disable signal, but only if said predetermined control code is not stored in said control register.
Claim 5
Dependent Claim
67 words
In a data processor which powers down in response to executing a power-down instruction, a method for selectively disabling said power-down instruction comprising the steps of: selectively storing in a predetermined location a control code indicating that said power-down instruction is to be disabled; and preventing said processor from powering-down in response to executing said instruction if said control code has been stored in said predetermined location.
Claim 6
Dependent Claim
67 words
In a data processor which powers down in response to executing a power-down instruction, a method for selectively disabling said power-down instruction comprising the steps of: selectively storing in a predetermined location a control code indicating that said power-down instruction is to be disabled; and preventing said processor from powering-down in response to executing said instruction if said control code has been stored in said predetermined location.
Claim 7
Dependent Claim
183 words
In a data processor comprising: oscillator means for providing a periodic clock signal except in response to receiving a power-down signal; reset means for providing a reset signal in response to a predetermined condition; and instruction execution control means, operative in synchronism with said clock signal, for receiving each of a plurality of different instructions comprising an instruction stream, and, in response to receiving a predetermined power-down instruction in said instruction stream, providing said power-down signal to said oscillator means to terminate said clock signal until said reset means next provides said reset signal, said instruction execution control means proceeding to a next instruction in said instruction stream only upon resumption of said clock signal; a method for selectively disabling said power-down instruction, comprising: storing a predetermined control code in response to said instruction execution control means receiving a different predetermined one of said instructions in said instruction stream; and in response to said control code being stored in said control register means, preventing said instruction execution control means from providing said power-down signal to said oscillator in response to said power-down instruction.
Claim 8
Dependent Claim
183 words
In a data processor comprising: oscillator means for providing a periodic clock signal except in response to receiving a power-down signal; reset means for providing a reset signal in response to a predetermined condition; and instruction execution control means, operative in synchronism with said clock signal, for receiving each of a plurality of different instructions comprising an instruction stream, and, in response to receiving a predetermined power-down instruction in said instruction stream, providing said power-down signal to said oscillator means to terminate said clock signal until said reset means next provides said reset signal, said instruction execution control means proceeding to a next instruction in said instruction stream only upon resumption of said clock signal; a method for selectively disabling said power-down instruction, comprising: storing a predetermined control code in response to said instruction execution control means receiving a different predetermined one of said instructions in said instruction stream; and in response to said control code being stored in said control register means, preventing said instruction execution control means from providing said power-down signal to said oscillator in response to said power-down instruction.
References Cited (Backward Citations)
US4137563A
Cited
US4204249A
Cited
US4203153A
Cited
US4279020A
Cited
US4381552A
Cited
US4365290A
Cited
US4293927A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |