Semiconductor memory device constituted by single transistor type non-volatile cells and facilitated for both electrical erasing and writing of data

Claim 2

A semiconductor memory device including a memory cell comprised of a single transistor, said memory cell comprising: a floating gate electrode formed over a main surface of a semiconductor substrate; a control gate electrode formed over said floating gate electrode; a first gate insulating film formed between said main surface and said floating gate electrode; a second gate insulating film formed between said floating gate electrode and said control gate electrode; a channel forming region formed in said semiconductor substrate and formed under said floating gate electrode; and a first semiconductor region and a second semiconductor region both of which are formed in said semiconductor substrate and are of n-type conductivity, wherein said channel forming region is formed between said first semiconductor region and said second semiconductor region and is of p-type conductivity, wherein said first and said second semiconductor regions are extended under said floating gate electrode, wherein electrons stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film in a data erasing operation, wherein hot electrons which are generated in said semiconductor substrate are injected into said floating gate electrode in a data writing operation, wherein said first semiconductor region has an impurity concentration higher than that of said second semiconductor region such that a surface depletion of said first semiconductor region is decreased when a first positive voltage and a first voltage lower than said first positive voltage are applied to said first semiconductor region and said control gate electrode, respectively, in said data erasing operation, and wherein said second semiconductor region has an impurity concentration such that said hot electrons are generated when a second positive voltage and a third positive voltage are applied to said control gate electrode and said second semiconductor region, respectively, indicating selection of said memory cell in said data writing operation, and tunneling of said electrons from said floating gate electrode to said second semiconductor region through said first gate insulating film is decreased by the forming of a surface depletion of said second semiconductor region when a second voltage, lower than said second positive voltage, and said third positive voltage are applied to said control gate electrode and said second semiconductor region, respectively, indicating that said memory cell is to remain unselected in said data writing operation.

Claim 3

A semiconductor memory device according to claim 1, further including: word lines formed over said main surface; data lines formed over said main surface; and a plurality of said memory cells, each of said word lines being electrically connected to said control gate electrodes of associated ones of said memory cells, and each of said data lines being electrically connected to said second semiconductor regions of associated ones of said memory cells, wherein said second voltage is a ground potential, and wherein said second positive voltage, said third positive voltage, and said second voltage are applied to one of said word lines, to one of said data lines, and to the remaining ones of said word lines, respectively, in said data writing operation, whereby said second positive voltage and said third positive voltage are applied to said selected memory cell, and said second voltage and said third positive voltage are applied to memory cells which are to remain unselected.

Claim 4

A semiconductor memory device according to claim 2, wherein an overlap area, in a plane view in parallel with said main surface, between said floating gate electrode and said first semiconductor region is greater than an overlap area, in a plane view in parallel with said main surface, between said floating gate electrode and said second semiconductor region.

Claim 5

A semiconductor memory device according to claim 1, wherein said first gate insulating film has a predetermined film thickness so as to permit electron tunneling through said first gate insulating film.

Claim 6

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a plurality of memory cells each of which is comprised of a single transistor, each memory cell including a floating gate electrode formed over said main surface, a control gate electrode formed over said floating gate electrode, a first gate insulating film formed between said main surface and said floating gate electrode, a second gate insulating film formed between said floating gate electrode and said control gate electrode, a channel forming region formed in said semiconductor substrate and formed under said floating gate electrode, and a first semiconductor region and a second semiconductor region formed in said semiconductor substrate, wherein said channel forming region is formed between said first semiconductor region and said second semiconductor region and is of p-type conductivity, and wherein said first and said second semiconductor regions are of n-type conductivity and are extended under said floating gate electrode, respectively; word lines formed over said main surface; and data lines formed over said main surface, wherein said word lines and said data lines are electrically connected to the control gate electrodes and the second semiconductor regions of associated ones of said memory cells, respectively, in such a manner that each combination of one of said word lines and one of said data lines defines a different one of said memory cells, wherein a first positive voltage and a first voltage lower than said first positive voltage are applied to said first semiconductor region and said control gate electrode, respectively, of ones of said memory cells selected for erasure, in a data erasing operation, to transfer electrons stored in said floating gate electrode from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film, wherein a second positive voltage, a third positive voltage and a second voltage lower than said second positive voltage are applied to one of said word lines, to one of said data lines, and to the remaining ones of said word lines, respectively, indicating selection, in a data writing operation, of that memory cell which is electrically connected to the word line and data line applied with said second positive voltage and said third positive voltage, respectively, wherein, in each of said memory cells, an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region such that a surface depletion of said first semiconductor region is decreased in said data erasing operation, and wherein, in each of said memory cells, said second semiconductor region has an impurity concentration such that hot electrons to be injected into said floating gate electrode are generated in a selected memory cell in said data writing operation, and tunneling of said electrons from said floating gate electrode to said second semiconductor region through said first gate insulating film is decreased by the forming of a surface depletion of said second semiconductor region in those of said memory cells which are electrically connected to both said one of said data lines and said remaining ones of said word lines in said data writing operation.

Claim 7

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a plurality of memory cells each of which is comprised of a single transistor, each memory cell including a floating gate electrode formed over said main surface, a control gate electrode formed over said floating gate electrode, a first gate insulating film formed between said main surface and said floating gate electrode, a second gate insulating film formed between said floating gate electrode and said control gate electrode, a channel forming region formed in said semiconductor substrate and formed under said floating gate electrode, and a first semiconductor region and a second semiconductor region formed in said semiconductor substrate, wherein said channel forming region is formed between said first semiconductor region and said second semiconductor region and is of p-type conductivity, and wherein said first and said second semiconductor regions are of n-type conductivity and are extended under said floating gate electrode, respectively; word lines formed over said main surface; and data lines formed over said main surface, wherein said word lines and said data lines are electrically connected to the control gate electrodes and the second semiconductor regions of associated ones of said memory cells, respectively, in such a manner that each combination of one of said word lines and one of said data lines defines a different one of said memory cells, wherein a first positive voltage and a first voltage lower than said first positive voltage are applied to said first semiconductor region and said control gate electrode, respectively, of ones of said memory cells selected for erasure, in a data erasing operation, to transfer electrons stored in said floating gate electrode from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film, wherein a second positive voltage, a third positive voltage and a second voltage lower than said second positive voltage are applied to one of said word lines, to one of said data lines, and to the remaining ones of said word lines, respectively, indicating selection, in a data writing operation, of that memory cell which is electrically connected to the word line and data line applied with said second positive voltage and said third positive voltage, respectively, wherein, in each of said memory cells, an impurity concentration of said first semiconductor region is higher than that of said second semiconductor region such that a surface depletion of said first semiconductor region is decreased in said data erasing operation, and wherein, in each of said memory cells, said second semiconductor region has an impurity concentration such that hot electrons to be injected into said floating gate electrode are generated in a selected memory cell in said data writing operation, and tunneling of said electrons from said floating gate electrode to said second semiconductor region through said first gate insulating film is decreased by the forming of a surface depletion of said second semiconductor region in those of said memory cells which are electrically connected to both said one of said data lines and said remaining ones of said word lines in said data writing operation.

Claim 8

A semiconductor memory device according to claim 5, wherein said second voltage is a ground potential.

Claim 9

A semiconductor memory device according to claim 5, wherein an overlap area between said floating gate electrode and said first semiconductor region is greater than an overlap area between said floating gate electrode and said second semiconductor region.

Claim 10

A semiconductor memory device according to claim 7, wherein a coupling capacitance between said floating gate electrode and said first semiconductor region is greater than a coupling capacitance between said floating gate electrode and said second semiconductor region.

Claim 11

A semiconductor memory device according to claim 8, wherein a junction depth of said first semiconductor region, with respect to the main surface of said semiconductor substrate, is greater than that of said second semiconductor region.

Claim 12

A semiconductor memory device according to claim 9, wherein said second voltage is a ground potential.

Claim 13

A semiconductor memory device according to claim 7, wherein said second voltage is a ground potential.

Claim 14

A semiconductor memory device according to claim 5, wherein said first gate insulating film has a predetermined film thickness so as to permit electron tunneling through said first gate insulating film.

Claim 15

A semiconductor memory device including a memory cell comprised of a single transistor, said memory cell comprising: a floating gate electrode formed over a main surface of a semiconductor substrate; a control gate electrode formed over said floating gate electrode; a first gate insulating film formed between said main surface and said floating gate electrode; a second gate insulating film formed between said floating gate electrode and said control gate electrode; a channel forming region formed in said semiconductor substrate and formed under said floating gate electrode; and a first semiconductor region and a second semiconductor region both of which are formed in said semiconductor substrate and are of n-type conductivity, wherein said channel forming region is formed between said first semiconductor region and said second semiconductor region and is of p-type conductivity, wherein said first and said second semiconductor regions are extended under said floating gate electrode in a manner in which an overlap area effected between said floating gate electrode and said first semiconductor region is greater than an overlap area effected between said floating gate electrode and said second semiconductor region, wherein electrons stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film in a data erasing operation, wherein hot electrons which are generated in said semiconductor substrate are insected into said floating gate electrode in a data writing operation, wherein said first semiconductor region has an impurity concentration higher than that of said second semiconductor region such that a surface depletion of said first semiconductor region is decreased when a first positive voltage and a first voltage lower than said first positive voltage are applied to said first semiconductor region and said control gate electrode, respectively, in said data erasing operation, and wherein said second semiconductor region has an impurity concentration such that said hot electrons are generated when a second positive voltage and a third positive voltage are applied to said control gate electrode and said second semiconductor region, respectively, indicating selection of said memory cell in said data writing operation, and tunneling of said electrons from said floating gate electrode to said second semiconductor region through said first gate insulating film is decreased by the forming of a surface depletion of said second semiconductor region when a second voltage, lower than said second positive voltage, and said third positive voltage are applied to said control gate electrode and said second semiconductor region, respectively, indicating that said memory cell is to remain unselected in said data writing operation.

Claim 16

A semiconductor memory device including a memory cell comprised of a single transistor, said memory cell comprising: a floating gate electrode formed over a main surface of a semiconductor substrate; a control gate electrode formed over said floating gate electrode; a first gate insulating film formed between said main surface and said floating gate electrode; a second gate insulating film formed between said floating gate electrode and said control gate electrode; a channel forming region formed in said semiconductor substrate and formed under said floating gate electrode; and a first semiconductor region and a second semiconductor region both of which are formed in said semiconductor substrate and are of n-type conductivity, wherein said channel forming region is formed between said first semiconductor region and said second semiconductor region and is of p-type conductivity, wherein said first and said second semiconductor regions are extended under said floating gate electrode in a manner in which an overlap area effected between said floating gate electrode and said first semiconductor region is greater than an overlap area effected between said floating gate electrode and said second semiconductor region, wherein electrons stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film in a data erasing operation, wherein hot electrons which are generated in said semiconductor substrate are insected into said floating gate electrode in a data writing operation, wherein said first semiconductor region has an impurity concentration higher than that of said second semiconductor region such that a surface depletion of said first semiconductor region is decreased when a first positive voltage and a first voltage lower than said first positive voltage are applied to said first semiconductor region and said control gate electrode, respectively, in said data erasing operation, and wherein said second semiconductor region has an impurity concentration such that said hot electrons are generated when a second positive voltage and a third positive voltage are applied to said control gate electrode and said second semiconductor region, respectively, indicating selection of said memory cell in said data writing operation, and tunneling of said electrons from said floating gate electrode to said second semiconductor region through said first gate insulating film is decreased by the forming of a surface depletion of said second semiconductor region when a second voltage, lower than said second positive voltage, and said third positive voltage are applied to said control gate electrode and said second semiconductor region, respectively, indicating that said memory cell is to remain unselected in said data writing operation.

Claim 17

A semiconductor memory device according to claim 13, wherein a coupling capacitance between said floating gate electrode and said first semiconductor region is greater than a coupling capacitance between said floating gate electrode and said second semiconductor region.

Claim 18

A semiconductor memory device according to claim 14, wherein a junction depth of said first semiconductor region, with respect to the main surface of said semiconductor substrate, is greater than that of said second semiconductor region.

Claim 19

A semiconductor memory device including a memory cell constituted by a single transistor, said memory cell comprising: a floating gate electrode formed over a main surface of a semiconductor substrate; a control gate electrode formed over said floating gate electrode; a first gate insulating film formed between said main surface and said floating gate electrode; a second gate insulating film formed between said floating gate electrode and said control gate electrode; a channel forming region formed in said semiconductor substrate and formed under said floating gate electrode; and a first semiconductor region and a second semiconductor region formed in said semiconductor substrate, said channel forming region being formed between said first semiconductor region and said second semiconductor region, and said first and said second semiconductor region having the same conductivity type and extending under said floating gate electrode, respectively, wherein said first semiconductor region has an impurity concentration higher than that of said second semiconductor region, wherein an overlap area between said floating gate electrode and said first semiconductor region is greater than an overlap area between said floating gate electrode and said second semiconductor region, wherein electrons stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film in a data erasing operation, wherein the impurity concentration of said first semiconductor region is such that a surface depletion of said first semiconductor region is decreased in said data erasing operation, and wherein the impurity concentration of said second semiconductor region is such that hot electrons to be injected into said floating gate electrode are generated in a data writing operation.

Claim 20

A semiconductor memory device including a memory cell constituted by a single transistor, said memory cell comprising: a floating gate electrode formed over a main surface of a semiconductor substrate; a control gate electrode formed over said floating gate electrode; a first gate insulating film formed between said main surface and said floating gate electrode; a second gate insulating film formed between said floating gate electrode and said control gate electrode; a channel forming region formed in said semiconductor substrate and formed under said floating gate electrode; and a first semiconductor region and a second semiconductor region formed in said semiconductor substrate, said channel forming region being formed between said first semiconductor region and said second semiconductor region, and said first and said second semiconductor region having the same conductivity type and extending under said floating gate electrode, respectively, wherein said first semiconductor region has an impurity concentration higher than that of said second semiconductor region, wherein an overlap area between said floating gate electrode and said first semiconductor region is greater than an overlap area between said floating gate electrode and said second semiconductor region, wherein electrons stored in said floating gate electrode are transferred from said floating gate electrode to said first semiconductor region by tunneling through said first gate insulating film in a data erasing operation, wherein the impurity concentration of said first semiconductor region is such that a surface depletion of said first semiconductor region is decreased in said data erasing operation, and wherein the impurity concentration of said second semiconductor region is such that hot electrons to be injected into said floating gate electrode are generated in a data writing operation.

Claim 21

A semiconductor memory device according to claim 16, wherein a coupling capacitance between said floating gate electrode and said first semiconductor region is greater than a coupling capacitance between said floating gate electrode and said second semiconductor region.

Claim 22

A semiconductor memory device according to claim 17, wherein a junction depth of said first semiconductor region, with respect to the main surface of said semiconductor substrate, is greater than that of said second semiconductor region.

Claim 23

A semiconductor memory device according to claim 18, wherein said first gate insulating film has a predetermined film thickness so as to permit electron tunneling through said first gate insulating film.

Claim 24

A semiconductor memory device according to claim 17, wherein said first gate insulating film has a predetermined film thickness so as to permit electron tunneling through said first gate insulating film.