Semiconductor integrated circuit including test circuit

Claim 2

A test apparatus for a semiconductor integrated circuit, comprising: a first test circuit for outputting a current when a test is made; a first wiring line having a first end connected to said first test circuit; a first transistor having a current path with a first end connected to a second end of said first wiring line; a second transistor having a current path with a first end connected to a second end of the current path of said first transistor, said first and second transistors being simultaneously set in a conductive state when the test is made; a second wiring line having a first end connected to a second end of said second transistor; a second test circuit connected to a second end of said second wiring line, said second test circuit detecting a current which is output from said first test circuit when the test is made and which is supplied thereto by way of said first and second transistors and said first and second wiring lines; and a third wiring line located between said second end of said first wiring line and said first end of said second wiring line, for transmitting a signal produced by said semiconductor integrated circuit during a normal operation mode, said third wiring line located on a first level which is different from a second level on which said first transistor and said second transistor are arranged, wherein said first and second wiring lines a smaller capacitance when said first and second transistors are set in an OFF sate than when said first and second transistors are set in an ON state.

Claim 3

The apparatus according to claim 1, wherein said first and second transistors are located below said third wiring line.

Claim 4

The apparatus according to claim 1, wherein said second wiring line is a data bus to which circuit elements are connected.

Claim 5

A test apparatus for a semiconductor integrated circuit, comprising: a first test circuit for outputting a current when a test is made; a first wiring line having a first end connected to said first test circuit; a first transistor having a current path with a first end connected to a second end of said first wiring line; a plurality of second transistors each having a current path with a first end connected to a second end of the current path of said first transistor; a plurality of second wiring lines each having a first end connected to a second end of one of said second transistors, respectively; a plurality of second test circuits each connected to a second end of one of said second wiring lines, respectively, said second test circuits detecting a current which is output from said first test circuit when the test is made and which is supplied thereto by way of said first transistor, said second transistors, said first wiring line, and said second wiring lines; control means for setting simultaneously said first transistor and at least one of said second transistors in a conductive state when the test is made, and for setting said first transistor and said second transistors in an OFF state when said semiconductor integrated circuit is operated in a normal operation mode; and a third wiring line located between said second end of said first wiring line and said first end of said second wiring line, for transmitting a signal produced by said semiconductor integrated circuit during the normal operation mode, said third wiring line located on a first level which is different from a second level on which said first transistor and said second transistor are arranged, wherein said first and second wiring lines have a smaller capacitance when said first and second transistors are set in an OFF state than when said first and second transistors are set in an ON state.

Claim 6

A test apparatus for a semiconductor integrated circuit, comprising: a first test circuit for outputting a current when a test is made; a first wiring line having a first end connected to said first test circuit; a first transistor having a current path with a first end connected to a second end of said first wiring line; a plurality of second transistors each having a current path with a first end connected to a second end of the current path of said first transistor; a plurality of second wiring lines each having a first end connected to a second end of one of said second transistors, respectively; a plurality of second test circuits each connected to a second end of one of said second wiring lines, respectively, said second test circuits detecting a current which is output from said first test circuit when the test is made and which is supplied thereto by way of said first transistor, said second transistors, said first wiring line, and said second wiring lines; control means for setting simultaneously said first transistor and at least one of said second transistors in a conductive state when the test is made, and for setting said first transistor and said second transistors in an OFF state when said semiconductor integrated circuit is operated in a normal operation mode; and a third wiring line located between said second end of said first wiring line and said first end of said second wiring line, for transmitting a signal produced by said semiconductor integrated circuit during the normal operation mode, said third wiring line located on a first level which is different from a second level on which said first transistor and said second transistor are arranged, wherein said first and second wiring lines have a smaller capacitance when said first and second transistors are set in an OFF state than when said first and second transistors are set in an ON state.

Claim 7

The apparatus according to claim 4, wherein said control means simultaneously sets said first transistor and said second transistors in an ON state when the test is made.

Claim 8

The apparatus according to claim 4, wherein said control means sets said first transistor and one of said second transistors in an ON state when the test is made.

Claim 9

The apparatus according to claim 4, wherein said first transistor and said second transistors are located below said third wiring line.

Claim 10

The apparatus according to claim 4, wherein each of said second wiring lines is a data bus to which circuit elements are connected.

Claim 11

A test apparatus for a semiconductor integrated circuit, comprising: a first wiring line; a second wiring line; a first test circuit connected to a first end of said first wiring line, for outputting a current when a test is made; a second test circuit connected to a first end of said second wiring line; a plurality of transistors having current paths connected in series between a second end of said first wiring line and a second end of said second wiring line, said transistors being simultaneously set in a conductive state when the test is made, thereby permitting the current output from said first test circuit and flowing through said first wiring line to be supplied to said second test circuit by way of said second wiring line, said second test circuit detecting a current supplied thereto through said second wiring line when the test is made; and a third wiring line located between said second end of said first wiring line and said second end of said second wiring line, for transmitting a signal produced by said semiconductor integrated circuit during a normal operation mode, said third wiring line located on a first level which is different from a second level on which said transistors are arranged, wherein said first and second wiring lines have a smaller capacitance when said transistors are set in an OFF state than when said transistors are set in an ON state.

Claim 12

A test apparatus for a semiconductor integrated circuit, comprising: a first wiring line; a second wiring line; a first test circuit connected to a first end of said first wiring line, for outputting a current when a test is made; a second test circuit connected to a first end of said second wiring line; a plurality of transistors having current paths connected in series between a second end of said first wiring line and a second end of said second wiring line, said transistors being simultaneously set in a conductive state when the test is made, thereby permitting the current output from said first test circuit and flowing through said first wiring line to be supplied to said second test circuit by way of said second wiring line, said second test circuit detecting a current supplied thereto through said second wiring line when the test is made; and a third wiring line located between said second end of said first wiring line and said second end of said second wiring line, for transmitting a signal produced by said semiconductor integrated circuit during a normal operation mode, said third wiring line located on a first level which is different from a second level on which said transistors are arranged, wherein said first and second wiring lines have a smaller capacitance when said transistors are set in an OFF state than when said transistors are set in an ON state.

Claim 13

The apparatus according to claim 9, wherein said transistors are located below said third wiring line.

Claim 14

The apparatus according to claim 9, wherein said second wiring line is a data bus to which circuit elements are connected.

Claim 15

The apparatus according to claim 9, wherein at least two of said transistors are conductive in the test mode.

Claim 16

The apparatus according to claim 1, further including a control means for controlling said first and second transistors to be in an ON state during a test mode, wherein said first and second test circuits are electrically connected, and to be in an OFF state during a normal operation mode, wherein said first and second test circuits are not electrically connected.

Claim 17

A test apparatus for a semiconductor integrated circuit, comprising: a first test circuit for outputting a current when a test is made; a first wiring line having a first end connected to said first test circuit; a first transistor having a current path with a first end connected to a second end of said first wiring line; a second transistor having a current path with a first end connected to a second end of the current path of said first transistor, said first and second transistors being simultaneously set in a conductive state when the test is made, and wherein said first and second transistors are formed in a substrate; a second wiring line having a first end connected to a second end of said second transistor; a second test circuit connected to a second end of said second wiring line, said second test circuit detecting a current which is output from said first test circuit when the test is made and which is supplied thereto by way of said first and second transistors and said first and second wiring lines; and a third wiring line located between said second end of said first wiring line and said first end of said second wiring line, for transmitting a signal produced by said semiconductor integrated circuit during a normal operation mode, said third wiring line located on an insulating layer formed on the substrate, wherein said first and second wiring lines have a smaller capacitance when said first and second transistor are set in an OFF state than when said first and second transistors are in an ON state.

Claim 18

A test apparatus for a semiconductor integrated circuit, comprising: a first test circuit for outputting a current when a test is made; a first wiring line having a first end connected to said first test circuit; a first transistor having a current path with a first end connected to a second end of said first wiring line; a second transistor having a current path with a first end connected to a second end of the current path of said first transistor, said first and second transistors being simultaneously set in a conductive state when the test is made, and wherein said first and second transistors are formed in a substrate; a second wiring line having a first end connected to a second end of said second transistor; a second test circuit connected to a second end of said second wiring line, said second test circuit detecting a current which is output from said first test circuit when the test is made and which is supplied thereto by way of said first and second transistors and said first and second wiring lines; and a third wiring line located between said second end of said first wiring line and said first end of said second wiring line, for transmitting a signal produced by said semiconductor integrated circuit during a normal operation mode, said third wiring line located on an insulating layer formed on the substrate, wherein said first and second wiring lines have a smaller capacitance when said first and second transistor are set in an OFF state than when said first and second transistors are in an ON state.