US5361033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
On chip bi-stable power-spike detection circuit
Assignee: Texas Instruments Inc
•
Filing: 1992-06-22
•
Granted: 1994-11-01
•
Expires: 2012-06-22
Abstract
Abstract A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/004; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; G11C29/00; G11C29/04; G11C5/00; G11C5/005; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
90 words
An error detection circuit comprising: a detection bi-stable circuit having a pair of cross-coupled inverters which is operable to store a first logic state; a pair of terminals for connecting power to the error detection circuit; and circuitry operable for producing a second logic state in said detection bi-stable circuit in connection with the occurrence of a spike in power which is delivered to the circuit, said circuitry comprising a pair of capacitors wherein each capacitor is connected between an output of one inverter and one of said power terminals.
Claim 2
Dependent Claim
90 words
An error detection circuit comprising: a detection bi-stable circuit having a pair of cross-coupled inverters which is operable to store a first logic state; a pair of terminals for connecting power to the error detection circuit; and circuitry operable for producing a second logic state in said detection bi-stable circuit in connection with the occurrence of a spike in power which is delivered to the circuit, said circuitry comprising a pair of capacitors wherein each capacitor is connected between an output of one inverter and one of said power terminals.
Claim 3
Dependent Claim
25 words
An error detection circuit as recited in claim 1 which further includes a sense amplifier operable to receive input from the outputs of said inverters.
Claim 4
Dependent Claim
19 words
An error detection circuit as recited in claim 2 which further includes a latch connected to said sense amplifier.
Claim 5
Dependent Claim
21 words
The error detection circuit of claim 1 further comprising circuitry for placing said detection bi-stable circuit in said first logic state.
Claim 6
Dependent Claim
39 words
The error detection circuit of claim 4 wherein said circuitry for placing said detection bi-stable circuit in said first logic state comprises a pair of pass transistors connected to said pair of cross-coupled inverters in the detection bi-stable circuit.
References Cited (Backward Citations)
US4578637A
Cited
US4670714A
Cited
US4685086A
Cited
US4794332A
Cited
US4789825A
Cited
US5070426A
Cited
US5084873A
Cited
US5157335A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |