US5084873A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip error detector
Assignee: Texas Instruments Inc
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Filing: 1989-01-27
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Granted: 1992-01-28
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Expires: 2009-01-27
Abstract
Abstract A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; G06; G06F; G06F11/00; G11C8/00; G11C8/20
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
80 words
A transient dose detection circuit comprising: a detection bi-stable circuit, including a memory cell, which is capable of storing a first logic state; circuitry operable for producing a second logic state in said detection bi-stable circuit in connection with the exposure of said transient dose detection circuit to sufficient levels of transient dose radiation; and a pair of bit lines connected to said memory cell, a favored state of said memory cell being caused by asymmetry on said bit lines.
Claim 2
Dependent Claim
80 words
A transient dose detection circuit comprising: a detection bi-stable circuit, including a memory cell, which is capable of storing a first logic state; circuitry operable for producing a second logic state in said detection bi-stable circuit in connection with the exposure of said transient dose detection circuit to sufficient levels of transient dose radiation; and a pair of bit lines connected to said memory cell, a favored state of said memory cell being caused by asymmetry on said bit lines.
Claim 3
Dependent Claim
28 words
A transient dose detection circuit as recited in claim 1 wherein the asymmetry on said bit lines substantially matches the worst case asymmetry in an associated memory array.
Claim 4
Dependent Claim
30 words
A transient dose detection circuit as recited in claim 1 wherein the asymmetry on said bit lines in adjustable relative to the worst case asymmetry in an associated memory array.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |