US5365167A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit device having signal discrimination circuit and method of testing the same
Assignee: Fujitsu VLSI Ltd
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Filing: 1994-02-03
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Granted: 1994-11-15
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Expires: 2014-02-03
Abstract
Abstract An integrated circuit device formed on a chip includes a pair of signal input terminals, a signal discriminating circuit having a pair of input terminals coupled to the signal input terminals, for comparing a data signal and a reference signal supplied through the input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a predetermined voltage is applied, and a voltage dividing circuit for dividing the predetermined voltage to thereby generate a test signal to be supplied to the signal discriminating circuit through the input terminals.
Inventors
- 👤 Masahiro Tanaka
- 👤 Kazuhiro Tomita
- 👤 Kazumi Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
245 words
A method of testing an integrated circuit device formed on a chip including; a pair of signal input terminals, signal discriminating means having a pair of input terminals coupled to said signal input terminals, for comparing a data signal and a reference signal supplied through said input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a first pair of test signals having a first potential difference is applied, voltage dividing means for dividing said first potential difference to thereby generate a second pair of test signals having a second potential difference less than said first potential difference, and switching means, provided between said voltage dividing means and said signal discriminating means, for selectively connecting said voltage dividing means and said signal discriminating means, said method comprising the steps of: connecting said voltage dividing means and said signal discrimination means through said switching means; supplying said pair of test signal terminals with said first pair of test signals forming said first potential difference; supplying said signal discriminating means with said second pair of test signals having said second voltage difference derived from said voltage dividing means; determining whether said signal discriminating means correctly discerns whether one of said second pair of test signals is higher than the other test signal; and disconnecting said voltage dividing means from said signal discriminating means by said switching means.
Claim 2
Independent Claim
245 words
A method of testing an integrated circuit device formed on a chip including; a pair of signal input terminals, signal discriminating means having a pair of input terminals coupled to said signal input terminals, for comparing a data signal and a reference signal supplied through said input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a first pair of test signals having a first potential difference is applied, voltage dividing means for dividing said first potential difference to thereby generate a second pair of test signals having a second potential difference less than said first potential difference, and switching means, provided between said voltage dividing means and said signal discriminating means, for selectively connecting said voltage dividing means and said signal discriminating means, said method comprising the steps of: connecting said voltage dividing means and said signal discrimination means through said switching means; supplying said pair of test signal terminals with said first pair of test signals forming said first potential difference; supplying said signal discriminating means with said second pair of test signals having said second voltage difference derived from said voltage dividing means; determining whether said signal discriminating means correctly discerns whether one of said second pair of test signals is higher than the other test signal; and disconnecting said voltage dividing means from said signal discriminating means by said switching means.
Claim 3
Dependent Claim
62 words
A method as claimed in claim 1, wherein said voltage dividing means includes a resistor network composed of a plurality of resistors connected in series, and wherein said resistor network has a pair of nodes through which said second pair of test signals is output, and said nodes are directly connected to said pair of input terminals of said signal discriminating means.
Claim 4
Dependent Claim
14 words
A method as claimed in claim 1, wherein said switching means includes switch contacts.
Claim 5
Dependent Claim
17 words
A method as claimed in claim 1, wherein said signal discriminating means includes an emitter-coupled logic circuit.
Claim 6
Dependent Claim
13 words
A method as claimed in claim 1, wherein said switching means includes fuses.
Claim 7
Dependent Claim
15 words
A method as claimed in claim 1, wherein said switching means includes field effect transistors.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-14 | 2006-05-16 | 2006-11-15 | $7700.00 | Window Closed / Lapsed |