Method of manufacturing a DRAM having peripheral circuitry in which source drain interconnection contact of a MOS transistor is made small by utilizing a pad layer

Claim 1

A method of manufacturing a DRAM including a memory cell having one MOS transistor and one stacked capacitor and a peripheral circuit including a MOS transistor, comprising the steps of: forming MOS transistors in a memory cell region and in a peripheral circuit region on a main surface of a semiconductor substrate; forming a first conductive layer on the entire surface of said semiconductor substrate and patterning the same to form an electrode layer connected to one of impurity regions of the MOS transistor in said memory cell and to form a first interconnection layer connected to one of impurity regions of the MOS transistor in said peripheral circuit extending at least above a gate electrode; covering surfaces of said electrode layer and said first interconnection layer with an insulating layer; and forming a second conductive layer on the entire surface of said semiconductor substrate and patterning the same to form a lower electrode of said capacitor connected to the other one of the impurity regions of the MOS transistor in said memory cell, and to form a second interconnection layer connected to the other one of the impurity region of the MOS transistor of said peripheral circuit extending at least above said gate electrode.

Claim 2

A method of manufacturing a DRAM including a memory cell having one MOS transistor and one stacked capacitor and a peripheral circuit including a MOS transistor, comprising the steps of: forming MOS transistors in a memory cell region and in a peripheral circuit region on a main surface of a semiconductor substrate; forming a first conductive layer on the entire surface of said semiconductor substrate and patterning the same to form an electrode layer connected to one of impurity regions of the MOS transistor in said memory cell and to form a first interconnection layer connected to one of impurity regions of the MOS transistor in said peripheral circuit extending at least above a gate electrode; covering surfaces of said electrode layer and said first interconnection layer with an insulating layer; and forming a second conductive layer on the entire surface of said semiconductor substrate and patterning the same to form a lower electrode of said capacitor connected to the other one of the impurity regions of the MOS transistor in said memory cell, and to form a second interconnection layer connected to the other one of the impurity region of the MOS transistor of said peripheral circuit extending at least above said gate electrode.