Stacked V-cell capacitor using a disposable outer digit line spacer

Claim 2

A process for fabricating a DRAM storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: forming a first insulating layer superadjacent existing substrate surface having a waveform-like topology; forming a second insulating layer superadjacent said first insulating layer; forming inner and outer spacers on walls of said digit lines from said first and second insulating layers, said outer spacers serving as disposable spacers; creating a self-aligned buried contact location at each said storage node junction in each said active area; forming a first conductive layer superadjacent said substrate surface assuming said waveform-like topology in response to existing topology, said first conductive layer making contact to said storage node junctions at said buried contact locations; patterning said first conductive layer to form a storage node plate at each said storage node junction, said storage node plate having a cross-sectional structure comprising a v-shaped structure residing inside a u-shaped structure; removing said disposable spacers; forming a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and forming a second conductive layer adjacent and coextensive said cell dielectric layer to form a cell plate.

Claim 3

A process as recited in claim 1, wherein said first insulating layer is oxide and said second insulating layer is nitride.

Claim 4

A process as recited in claim 1, wherein said first insulating layer is nitride and said second insulating layer is oxide.

Claim 5

A process as recited in claim 2, wherein said oxide layer is TEOS.

Claim 6

A process as recited in claim 3, wherein said oxide layer is TEOS.

Claim 7

A process as recited in claim 1, wherein said first and second insulating layers are deposited by chemical vapor deposition.

Claim 8

A process as recited in claim 1, wherein said first and second conductive layer are doped polysilicon.

Claim 9

A process as recited in claim 7, wherein said first conductive layer is deposited by low temperature deposition.

Claim 10

A process as recited in claim 1, wherein said cell dielectric layer is nitride.

Claim 11

A process for fabricating a DRAM storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: depositing a first oxide layer superadjacent existing substrate surface having a waveform-like topology; depositing a first nitride layer superadjacent said first oxide layer; etching said first oxide and said first nitride layers to form oxide and nitride spacers adjacent walls of said digit lines, said nitride spacers serving as disposable spacers; creating a self-aligned buried contact location at each said storage node junction in each said active area; depositing a first conductive polysilicon layer superadjacent said substrate surface assuming said waveform-like topology in response to existing topology, said first conductive polysilicon layer making contact to said storage node junctions at said buried contact locations; patterning said first conductive polysilicon layer to form a storage node plate at each said storage node junction, said storage node plate having a cross-sectional structure comprising a v-shaped structure residing inside a u-shaped structure; anisotropically etching said disposable spacers; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a second conductive polysilicon layer adjacent and coextensive said cell dielectric layer to form a cell plate.

Claim 12

A process for fabricating a DRAM storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the steps of: depositing a first oxide layer superadjacent existing substrate surface having a waveform-like topology; depositing a first nitride layer superadjacent said first oxide layer; etching said first oxide and said first nitride layers to form oxide and nitride spacers adjacent walls of said digit lines, said nitride spacers serving as disposable spacers; creating a self-aligned buried contact location at each said storage node junction in each said active area; depositing a first conductive polysilicon layer superadjacent said substrate surface assuming said waveform-like topology in response to existing topology, said first conductive polysilicon layer making contact to said storage node junctions at said buried contact locations; patterning said first conductive polysilicon layer to form a storage node plate at each said storage node junction, said storage node plate having a cross-sectional structure comprising a v-shaped structure residing inside a u-shaped structure; anisotropically etching said disposable spacers; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a second conductive polysilicon layer adjacent and coextensive said cell dielectric layer to form a cell plate.