Contact plug forming method

Claim 2

A semiconductor device manufacturing method comprising the steps of: forming a first conductive layer; forming an insulation film on said first conductive layer to cover said first conductive layer with said insulation film, the insulation film having an exposed surface opposite from said first conductive layer; selectively etching said insulation film on said first conductive layer to form a contact hole through the exposed surface and expose part of said first conductive layer in said contact hole; removing a natural oxide film from the part of said first conductive layer exposed within said contact hole by plasma etching using a halogen gas; exposing the resultant structure to a gas atmosphere containing halogen, separately from said natural oxide removing step, to purify the exposed surface of said insulation film and thereby inhibit deposition of contact plug material thereon, at temperatures in a range between room temperature and 400° C.; after the step of exposing the resultant structure, depositing and forming a contact plug on part of said first conductive layer exposed in said contact hole by selective chemical vapor deposition to fill in said contact hole; and forming a second conductive layer on the exposed surface of said insulation film to electrically connect said first and second conductive layers to each other via said contact plug.

Claim 3

A semiconductor device manufacturing method according to claim 1, wherein said contact plug contains refractory metal created by a reducing reaction of a compound of refractory metal.

Claim 4

A semiconductor device manufacturing method according to claim 2, wherein the temperature of the reducing reaction is set in a range of room temperature to 400° C.

Claim 5

A semiconductor device manufacturing method according to claim 1, wherein, during exposing the resulting structure, the gas containing halogen contains an inert gas as a carrier gas.

Claim 6

A semiconductor device manufacturing method according to claim 1, wherein, during exposing the resulting structure, the gas containing halogen contains at least one gas selected from a group consisting of F 2 , WF 6 , NF 3 , CF 4 , C 3 F 8 , CHF 3 , CH 3 F 2 , CCl 4 , BF 3 , SF 6 , HF, BCl 3 , ClF 4 and Cl 2 .

Claim 7

A semiconductor device manufacturing method according to claim 1, wherein said contact plug contains at least one material selected from a group consisting of tungsten, aluminum, gold, molybdenum and copper.

Claim 8

A semiconductor device manufacturing method according to claim 1, wherein said first conductive layer is selected from a group consisting of polysilicon, silicide, aluminum and impurity diffused layer.

Claim 9

A semiconductor device manufacturing method according to claim 1, wherein said second conductive layer is selected from a group consisting of polysilicon, silicide and aluminum.

Claim 10

A semiconductor device manufacturing method according to claim 1, wherein said insulation film is selected from a group consisting of boro-phospho silicate glass, phospho-silicate glass, tetraethyl orthosilicate and chemical vapor deposited-SiO 2 .

Claim 11

A semiconductor device manufacturing method comprising the steps of: forming a first insulation film on a semiconductor substrate; forming a first-level interconnection layer on said first insulation film; forming a second insulation film on said first insulation film and first-level interconnection layer, the second insulation film having an exposed surface opposite from said first-level interconection layer; selectively etching part of said second insulation film which lies on said first-level interconnection layer to form a contact hole through the exposed surface and expose part of said first-level interconnection layer in said contact hole; removing a natural oxide film from the part of said first-level interconnection layer exposed within said contact hole by plasma etching using a halogen gas; exposing said semiconductor substrate to a gas atmosphere containing halogen, separately from said natural oxide removing step, to purify the exposed surface of said second insulation film and thereby inhibit deposition of contact plug material thereon, at temperatures in a range between room temperature and 400° C.; after the step of exposing said semiconductor substrate, depositing and forming a contact plug formed of refractory metal created by a reducing reaction of a compound of refractory metal on part of said first-level interconnection layer which is exposed in said contact hole to fill in said contact hole; and forming a second-level interconnection layer on said second insulation film to electrically connect said first-level and second-level interconnection layers to each other via said contact plug.

Claim 12

A semiconductor device manufacturing method comprising the steps of: forming a first insulation film on a semiconductor substrate; forming a first-level interconnection layer on said first insulation film; forming a second insulation film on said first insulation film and first-level interconnection layer, the second insulation film having an exposed surface opposite from said first-level interconection layer; selectively etching part of said second insulation film which lies on said first-level interconnection layer to form a contact hole through the exposed surface and expose part of said first-level interconnection layer in said contact hole; removing a natural oxide film from the part of said first-level interconnection layer exposed within said contact hole by plasma etching using a halogen gas; exposing said semiconductor substrate to a gas atmosphere containing halogen, separately from said natural oxide removing step, to purify the exposed surface of said second insulation film and thereby inhibit deposition of contact plug material thereon, at temperatures in a range between room temperature and 400° C.; after the step of exposing said semiconductor substrate, depositing and forming a contact plug formed of refractory metal created by a reducing reaction of a compound of refractory metal on part of said first-level interconnection layer which is exposed in said contact hole to fill in said contact hole; and forming a second-level interconnection layer on said second insulation film to electrically connect said first-level and second-level interconnection layers to each other via said contact plug.

Claim 13

A semiconductor device manufacturing method according to claim 10, wherein the temperature of the reducing reaction is set in a range of room temperature to 400° C.

Claim 14

A semiconductor device manufacturing method according to claim 10, wherein, during the step of exposing the semiconductor substrate, the gas containing halogen contains an inert gas as a carrier gas.

Claim 15

A semiconductor device manufacturing method according to claim 10, wherein, during the step of exposing the semiconductor substrate, the gas containing halogen contains at least one gas selected from a group consisting of F 2 , WF 6 , NF 3 , CF 4 , C 3 F 8 , CHF 3 , CH 3 F 2 , CCl 4 , BF 3 , SF 6 , HF, BCl 3 , ClF 4 and Cl 2 .

Claim 16

A semiconductor device manufacturing method comprising the steps of: forming an impurity diffused layer in a semiconductor substrate; forming an insulation film on said semiconductor substrate; selectively etching part of said insulation film which lies on said impurity diffused layer to form a contact hole and expose part of said impurity diffused layer in said contact hole; removing a natural oxide film from the part of said impurity diffused layer exposed within said contact hole by plasma etching using a halogen gas; exposing said semicondutor substrate to a gas atmosphere containing halogen, separately from said natural oxide removal step, to purify an exposed surface of said insulation film and thereby inhibit deposition of contact plug material thereon, at temperatures in a range between room temperature and 400° C.; after the step of exposing said semiconductor substrate, depositing and forming a contact plug formed of refractory metal created by a reducing reaction of a compound of refractory metal on part of said impurity diffused layer which is exposed in said contact hole to fill in said contact hole; and forming an interconnection layer on said insulation film to electrically connect said impurity diffused layer and said interconnection layer to each other via said contact plug.

Claim 17

A semiconductor device manufacturing method comprising the steps of: forming an impurity diffused layer in a semiconductor substrate; forming an insulation film on said semiconductor substrate; selectively etching part of said insulation film which lies on said impurity diffused layer to form a contact hole and expose part of said impurity diffused layer in said contact hole; removing a natural oxide film from the part of said impurity diffused layer exposed within said contact hole by plasma etching using a halogen gas; exposing said semicondutor substrate to a gas atmosphere containing halogen, separately from said natural oxide removal step, to purify an exposed surface of said insulation film and thereby inhibit deposition of contact plug material thereon, at temperatures in a range between room temperature and 400° C.; after the step of exposing said semiconductor substrate, depositing and forming a contact plug formed of refractory metal created by a reducing reaction of a compound of refractory metal on part of said impurity diffused layer which is exposed in said contact hole to fill in said contact hole; and forming an interconnection layer on said insulation film to electrically connect said impurity diffused layer and said interconnection layer to each other via said contact plug.

Claim 18

A semiconductor device manufacturing method according to claim 14, further comprising a step of forming a semiconductor element in said semiconductor substrate.

Claim 19

A semiconductor device manufacturing method according to claim 14, wherein said impurity diffused layer is part of an active region of a semiconductor element.

Claim 20

A semiconductor device manufacturing method according to claim 14, wherein the temperature of the reducing reaction is set in a range of room temperature to 400° C.

Claim 21

A semiconductor device manufacturing method according to claim 14, wherein, during the step of exposing the semiconductor substrate, the gas containing halogen contains an inert gas as a carrier gas.

Claim 22

A semiconductor device manufacturing method according to claim 14, wherein, during the step of exposing the semiconductor substrate, the gas containing halogen contains at least one gas selected from a group consisting of F 2 , WF 6 , NF 3 , CF 4 , C 3 F 8 , CHF 3 , CH 3 F 2 , CCl 4 , BF 3 , SF 6 , HF, BCl 3 , ClF 4 and Cl 2 .