Single-chip microcomputer system having address space allocation hardware for different modes

Claim 1

A microcomputer system, comprising: a single-chip microcomputer, in which a CPU, executing a program, and internal resources, including an internal ROM being accessed through execution of said program by said CPU, are configured on one chip, said internal ROM having an address space including an interrupt vector area for storing addresses of programs for interrupt processing and areas whereto addresses of said internal ROM are allocated; and external resources connected with said single-chip microcomputer and being accessed through execution of the program by said CPU; wherein said system can operate in either a first mode under which said CPU can access only said internal resources and said internal ROM is allocated to a first area in said address space, or a second mode under which said CPU can access both of said internal resources and said external resources and said internal ROM is allocated to a second area in said address space, said second area excluding said interrupt area, further comprising: address decoding means for decoding an address outputted from said CPU and accessing said address space in one of said first and second modes, address space changing-over means for making said address decoding means access said first area of said internal ROM when a first value indicating said first mode is set as an address space changing-over bit, and for making said address decoding means access said second area of said internal ROM when a second value indicating said second mode is set as said address space changing-over bit.