US4374411A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Relocatable read only memory
Assignee: Telogy Networks Inc
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Filing: 1980-02-14
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Granted: 1983-02-15
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Expires: 2000-02-14
Abstract
Abstract A read only memory apparatus for use in a byte oriented processor (10) includes a data selector (25) which responds to the first memory fetch of a memory reference instruction (40, 28) to provide a selected set of output bits (20) from a read only memory to a particular portion (22) of the processor data bus. The apparatus provides a set of replacement bits (26) to the same portion of the data bus (22) in response to each occurrence of detection (29, 30') of the most significant byte of a such memory reference instruction being provided to the data bus. The replacement bits occur in the most significant byte of the address referred to in the memory reference instruction and prevents the processor's program counter from jumping out of the address space alloted to the read only memory. In the preferred form, the same set of switches (17) used with an address decoder (15) to define the location of the ROM circuit in the address space of the processor's memory also provides replacement bits.
Inventors
- 👤 Dale A. Heatherington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:24
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/261; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0669
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
159 words
In a read only memory, adapted to be used with an L-bit byte, byte oriented processor, said processor being characterized by a data bus for at least presenting outputs from said memory to an address register in said processor, by an instruction set including memory reference instructions of M bytes requiring M fetches to memory wherein the Mth fetched byte of each of said memory reference instructions is a most significant byte, L and M being positive integers, said processor providing predetermined status signals, the improvement comprising: location means for providing N replacement address bits, N being an integer greater than zero and less than or equal to a L; means responsive to said status signal for providing a most significant byte signal in response to an Mth fetch of a said memory reference instruction; and data selector means for providing said N replacement bits to lines of said data bus in response to said most significant byte signal.
Claim 2
Dependent Claim
159 words
In a read only memory, adapted to be used with an L-bit byte, byte oriented processor, said processor being characterized by a data bus for at least presenting outputs from said memory to an address register in said processor, by an instruction set including memory reference instructions of M bytes requiring M fetches to memory wherein the Mth fetched byte of each of said memory reference instructions is a most significant byte, L and M being positive integers, said processor providing predetermined status signals, the improvement comprising: location means for providing N replacement address bits, N being an integer greater than zero and less than or equal to a L; means responsive to said status signal for providing a most significant byte signal in response to an Mth fetch of a said memory reference instruction; and data selector means for providing said N replacement bits to lines of said data bus in response to said most significant byte signal.
Claim 3
Dependent Claim
59 words
A read only memory as recited in claim 1 further comprising an address decoder for comparing N address bits from said processor which appear on an address bus to said N replacement bits from said location means including means for providing a memory enabling signal when said N adress bits bear a predetermined relationship to said N replacement bits.
Claim 4
Dependent Claim
18 words
A read only memory as recited in claim 2 wherein said location means comprises a plurality of switches.
Claim 5
Dependent Claim
38 words
A read only memory as recited in claim 1 including means for connecting said data selector means to said data bus to provide said N replacement bits to the N most significant bit lines of said data bus.
Claim 6
Dependent Claim
270 words
In a memory apparatus for use with an L bit byte, byte oriented processor having an instruction set characterized by M byte memory reference instructions wherein the Mth byte of said memory reference instruction is the most significant byte of the memory reference of said memory reference instruction, said processor including an address bus and a data bus for at least presenting output signals from said memory apparatus to an address register in said processor, M and L being integers, the improvement of: a set of switches for establishing a set of N block location bits, N being an integer greater than zero and less than or equal to L; a N bit address block decoder for providing an enable signal in response to a predetermined set of address bits from said processor which appear on said address bus which bear a predetermined relationship to said block location bits; said memory apparatus including means for operatively connecting to said address bus in response to said enable signal; control means for providing a first select signal upon each occurrence of a first memory fetch of a said memory reference instruction from said processor and for providing a second select signal in response to each occurrence of an Mth memory fetch of a said memory reference instruction from said processor; and data selector means for providing N bits of an output from said memory apparatus to N lines of said data bus in response to said first select signal and for providing said N block location bits to said N lines of said data bus in response to said second select signal.
Claim 7
Dependent Claim
270 words
In a memory apparatus for use with an L bit byte, byte oriented processor having an instruction set characterized by M byte memory reference instructions wherein the Mth byte of said memory reference instruction is the most significant byte of the memory reference of said memory reference instruction, said processor including an address bus and a data bus for at least presenting output signals from said memory apparatus to an address register in said processor, M and L being integers, the improvement of: a set of switches for establishing a set of N block location bits, N being an integer greater than zero and less than or equal to L; a N bit address block decoder for providing an enable signal in response to a predetermined set of address bits from said processor which appear on said address bus which bear a predetermined relationship to said block location bits; said memory apparatus including means for operatively connecting to said address bus in response to said enable signal; control means for providing a first select signal upon each occurrence of a first memory fetch of a said memory reference instruction from said processor and for providing a second select signal in response to each occurrence of an Mth memory fetch of a said memory reference instruction from said processor; and data selector means for providing N bits of an output from said memory apparatus to N lines of said data bus in response to said first select signal and for providing said N block location bits to said N lines of said data bus in response to said second select signal.
Claim 8
Dependent Claim
16 words
A memory apparatus as recited in claim 5 wherein said memory is a read only memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-14 | 1986-08-16 | 1987-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-14 | 1990-08-16 | 1991-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-14 | 1994-08-16 | 1995-02-15 | $7700.00 | Window Closed / Lapsed |