Memory bank switching apparatus

Claim 2

A memory bank switching apparatus comprising: an address bus, a data bus and a control line; a plurality of memory banks consisting of ROMs and storing mutually different programs therein connected in parallel to said address bus, said data bus and said control line; a CPU for feeding an address signal to said address bus and a write control signal to said control line and for transmitting and receiving a data signal over said data bus; and a bank switching register connected to said CPU through said address bus, said data bus and said control signal line; said bank switching register, when addressed by said address bus, being responsive to the write control signal for storing therein a number corresponding to a selected one of said memory banks from said data bus; and said bank switching register being connected to said memory banks for enabling the selected memory bank and for disabling the non-selected memory bank or banks.

Claim 3

The memory bank switching apparatus as defined in claim 1, further comprising a decoder inserted between said bank switching register and each of said memory banks for decoding the content of said bank switching register and feeding a control signal to one of said memory banks selected according to the content of said register so as to effect access to said selected memory bank.

Claim 4

In an apparatus for switching a plurality of memory banks connected in parallel to an address bus, a data bus and a control line by first addressing said banks simultaneously by an address signal on the address bus and then applying a switching signal to the memory banks to select one of said memory banks alone, the improvement comprising: (a) a bank switching register connected to said address bus, said data bus and said control line for storing the numbers of said memory banks to effect access thereto; (b) means for outputting onto the address bus a specific address signal within a prescribed address scope for access to both said memory banks and said bank switching register, then outputting onto the data bus bank selecting data to be written in said bank switching register, and further outputting a write command onto the control signal line extending to said bank switching register; and (c) a decoder connected between said bank switching register and said memory banks for decoding the content of said bank switching register and transmitting a control signal to one of said memory banks selected according to said content so as to effect access thereto.

Claim 5

In an apparatus for switching a plurality of memory banks connected in parallel to an address bus, a data bus and a control line by first addressing said banks simultaneously by an address signal on the address bus and then applying a switching signal to the memory banks to select one of said memory banks alone, the improvement comprising: (a) a bank switching register connected to said address bus, said data bus and said control line for storing the numbers of said memory banks to effect access thereto; (b) means for outputting onto the address bus a specific address signal within a prescribed address scope for access to both said memory banks and said bank switching register, then outputting onto the data bus bank selecting data to be written in said bank switching register, and further outputting a write command onto the control signal line extending to said bank switching register; and (c) a decoder connected between said bank switching register and said memory banks for decoding the content of said bank switching register and transmitting a control signal to one of said memory banks selected according to said content so as to effect access thereto.