Memory bank addressing

Claim 2

The combination comprising: A. a memory having a plurality of memory banks, each of said memory banks including a plurality of storage locations; B. first means for addressing any one of said locations in a selected one of said memory banks; C. second means for addressing a first selected one of said memory banks; D. third means for addressing a second selected one of said memory banks; E. means for generating either a first signal or a second signal; F. first means, responsive to said first signal, for enabling said second means for addressing; and G. second means, responsive to said second signal, for enabling said third means for addressing.

Claim 3

The combination of claim 1 further comprising: A. means for generating an interrupt signal; and B. means, responsive to said interrupt signal, for enabling said second means for addressing to address a predetermined one of said memory banks.

Claim 4

The combination of claim 2 further comprising means, responsive to said interrupt signal, for enabling said third means for addressing to address said predetermined one of said memory banks.

Claim 5

The combination of claim 2 further comprising means, responsive to said interrupt signal, for enabling said third means for addressing to address another predetermined one of said memory banks.

Claim 6

The combination of claim 4 further comprising: A. means for generating a third signal following a response to said interrupt signal; and B. means, responsive to said third signal, for respectively restoring said second and third means for addressing with the addresses of said first and second selected ones of said memory banks.

Claim 7

The combination of claim 2 further comprising: A. means for generating a third signal following a response to said interrupt signal; and B. means, responsive to said third signal, for restoring said second means for addressing with the addresses of said first selected one of said memory banks.

Claim 8

A memory addressing system for addressing a memory having a plurality of memory banks, each of said memory banks including a plurality of storage locations, said system comprising: A. a memory address register coupled to address one storage location in one of said memory banks corresponding to an address word transferred to said address register; B. means for providing a first segment of said address word to said address register, said first segment indicating the address of a storage location to be addressed; C. a first register for storing a second segment of said address word; D. a second register for storing a second segment of said address word, said second segment in either said first or second registers indicating the address of a memory bank to be addressed; E. means for providing a bank select signal; and F. means, responsive to said bank select signal, for transferring the second segment in either said first or second registers to said address register.

Claim 9

A memory addressing system for addressing a memory having a plurality of memory banks, each of said memory banks including a plurality of storage locations, said system comprising: A. a memory address register coupled to address one storage location in one of said memory banks corresponding to an address word transferred to said address register; B. means for providing a first segment of said address word to said address register, said first segment indicating the address of a storage location to be addressed; C. a first register for storing a second segment of said address word; D. a second register for storing a second segment of said address word, said second segment in either said first or second registers indicating the address of a memory bank to be addressed; E. means for providing a bank select signal; and F. means, responsive to said bank select signal, for transferring the second segment in either said first or second registers to said address register.

Claim 10

The system of claim 7 further comprising: A. means for generating an interrupt signal; and B. means, responsive to said interrupt signal, for causing said second segment of said address word stored in either or both of said first and second registers to indicate the address of a predetermined one or ones of said memory banks.

Claim 11

The system of claim 7 further comprising: A. a third register; B. a fourth register; C. further storage means; D. means for generating a load signal; E. means, responsive to said load signal, for transferring the address or addresses of a certain one or different ones of said memory banks from said further storage means to said third and fourth registers respectively; F. means for generating a jump signal; G. first means, responsive to said jump signal, for transferring the address stored in said third register to said first register; and H. second means, responsive to said jump signal, for transferring the address stored in said fourth register to said second register.

Claim 12

The system of claim 9 further comprising: A. means for generating an interrupt signal; and B. means, responsive to said interrupt signal, for causing said second segment of said address word stored in either or both of said first and second registers to indicate the address of a predetermined one or ones of said memory banks.

Claim 13

The system of claim 10 wherein each of said first and second registers include a plurality of bistable storage means, each having a set and reset input and wherein said interrupt signal is received at either said set or reset inputs in order to generate the address of said predetermined one or ones of said memory banks in response to said interrupt signal.

Claim 14

The system of claim 10 further comprising: A. means for generating an unload signal; and B. means, responsive to said unload signal, for transferring the addresses stored in said third and fourth registers to said further storage means.