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US4839795A Expired / Lapsed US ⏱️ 0.0 years remaining

Interface circuit for single-chip microprocessor

Assignee: Mitsubishi Electric Corp
•
Filing: 1987-11-25
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Granted: 1989-06-13
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Expires: 2007-11-25
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Abstract

Abstract An interface circuit, having a single-chip microprocessor with program instructions in internal memory, includes switching devices between A-D (Analog to Digital) ports of the microprocessor and ports of the interface circuit for selectively connecting and disconnecting the microprocessor and interface ports. The interface circuit includes a connector through which address latch units and external memory having program instructions can be connected to the single-chip microprocessor. The connector provides for switch over of operation of the microprocessor from internal memory to external memory, and for operation of the switching devices. The connector provides for connection of an I/O (Input/Output) unit to provide input and output to ports of the interface circuit.

Inventors

  • 👤 Masahiko Iwaksaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 17:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814; G06F9/26; G06F9/262; G06F9/268

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 276 words
An interface circuit for a microprocessor having internal ROM memory with a first program therein, control input means for selecting operation in first and second modes, said microprocessor in the first mode operating in accordance with the first program in internal memory, said microprocessor in the second mode operating in accordance with a second program in external memory, an address-data port which in the first mode is operable as a data input or output port and in the second mode is operable in a multiplexing mode alternately to output address signals and to input or output program instructions or data from external memory and memory mapped devices, the interface circuit comprising, comprising: (a) an interface input and/or output port for functioning as the input and/or output port of the microprocessor; (b) switch means connected between the address-data port of the microprocessor and the interface input and/or output port so as to control conduction or shutting-off of passage of signals between the address-data port of the microprocessor and the interface input and/or output port; (c) connector means for connecting the address-data port of the microprocessor to external memory means, for connecting said control input means of the microprocessor to external circuitry to operate the microprocessor in the second mode, for connecting external circuitry which operates the switch means to shut-off passage of signals through the switch means, and for connecting an external I/O unit between the address-data port and the interface input and/or output port; and (d) biasing means for operating the switch means to render the switch means conductive in the absence of the connection of the external switch means operating circuitry by the connector means.
Claim 2
Dependent Claim 276 words
An interface circuit for a microprocessor having internal ROM memory with a first program therein, control input means for selecting operation in first and second modes, said microprocessor in the first mode operating in accordance with the first program in internal memory, said microprocessor in the second mode operating in accordance with a second program in external memory, an address-data port which in the first mode is operable as a data input or output port and in the second mode is operable in a multiplexing mode alternately to output address signals and to input or output program instructions or data from external memory and memory mapped devices, the interface circuit comprising, comprising: (a) an interface input and/or output port for functioning as the input and/or output port of the microprocessor; (b) switch means connected between the address-data port of the microprocessor and the interface input and/or output port so as to control conduction or shutting-off of passage of signals between the address-data port of the microprocessor and the interface input and/or output port; (c) connector means for connecting the address-data port of the microprocessor to external memory means, for connecting said control input means of the microprocessor to external circuitry to operate the microprocessor in the second mode, for connecting external circuitry which operates the switch means to shut-off passage of signals through the switch means, and for connecting an external I/O unit between the address-data port and the interface input and/or output port; and (d) biasing means for operating the switch means to render the switch means conductive in the absence of the connection of the external switch means operating circuitry by the connector means.
Claim 3
Dependent Claim 36 words
An interface circuit for a microprocessor as set forth in claim 1 in which said switch means has 3-state buffers wherein the external switch means operating circuitry produces a high impedance condition of the 3-state buffers.
Claim 4
Dependent Claim 53 words
An interface circuit for a microprocessor as set forth in claim 1 in which said switch means has selectors for selecting and outputting signals from the address-data ports of the microprocessor in response to the biasing means or signals from the external I/O unit in response to the external switch means operation circuitry.
Claim 5
Dependent Claim 52 words
An interface circuit for a microprocessor as set forth in any one of claims 1, 2, or 3 in which said external memory means has memory elements storing the second program therein, and a holding circuit for holding address information to read out the second program stored in said external memory elements.

References Cited (Backward Citations)

US3806878A Cited
US3766526A Cited
US3833930A Cited
US4442504A Cited
US4514805A Cited
US4628158A Cited
JPS5971557A Cited
JPS59216263A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-06-12 1992-12-12 1993-06-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-06-12 1996-12-12 1997-06-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-06-12 2000-12-12 2001-06-13 $7700.00 Window Closed / Lapsed

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