Abstract Diagnostics in a peripheral subsystem for a data processing system are performed on a concurrent basis with other programs in the data processing system. The peripheral subsystem has capabilities of generating indications for the data processing system representative of operational conditions that could be encountered; the data processing system is programmed to respond to said indications for diagnosing the operational capabilities of the connected peripheral subsystem. Included in the diagnostics are interface checking between the subsystem and the rest of the data processing system, device status, capability of stacking status, capability of handling nonstackable status, verifying enable/disable operation, and checking device busy status and the like.
In interfacing circuits for generating an anomalous indication from a subsystem in response to a requesting signal from a controlling data processing system interconnected with said subsystem via said interfacing circuits, means chaining said subsystem to a CPU, means supplying a flag signal, means selectively setting a diagnostic mode, memory means for maintaining a status indication and a flag signal, means gating said status indication, logic means responsive to said requesting signal and another signal to generate a gating signal, the improvement including in combination: AND circuit means jointly responsive to said requesting signal and a flag signal from said subsystem to supply an enabling signal, said subsystem capable of setting said flag signal only when chained to a CPU and in a diagnostic mode of operation, encoding means responsive to said status indication or to said enabling signal to generate a code permutation representing said status indication, and said gating means being responsive to said enabling signal or to said gating signal to gate said code permutation to said CPU.
Claim 2
Dependent Claim
171 words
In interfacing circuits for generating an anomalous indication from a subsystem in response to a requesting signal from a controlling data processing system interconnected with said subsystem via said interfacing circuits, means chaining said subsystem to a CPU, means supplying a flag signal, means selectively setting a diagnostic mode, memory means for maintaining a status indication and a flag signal, means gating said status indication, logic means responsive to said requesting signal and another signal to generate a gating signal, the improvement including in combination: AND circuit means jointly responsive to said requesting signal and a flag signal from said subsystem to supply an enabling signal, said subsystem capable of setting said flag signal only when chained to a CPU and in a diagnostic mode of operation, encoding means responsive to said status indication or to said enabling signal to generate a code permutation representing said status indication, and said gating means being responsive to said enabling signal or to said gating signal to gate said code permutation to said CPU.